fin12a Fairchild Semiconductor, fin12a Datasheet
fin12a
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fin12a Summary of contents
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... Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary) General Description The FIN12A is a 12-bit serializer capable of running a par- allel frequency range between 5MHz and 56MHz. The fre- quency range is selected by the S1 and S2 control signals. The bi-directional data flow is controlled through use of a direction (DIRI) control pin ...
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Functional Block Diagram Connection Diagram www.fairchildsemi.com Terminal Assignments for MLP (Top View) 2 Preliminary ...
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... Other layout orientations may require that traces or cables cross. Control Logic Circuitry The FIN12A has the ability to be used as a 12-bit Serializer or a 12-bit Deserializer. Terminals S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer ...
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Power-Down Mode Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state the PLL and references will be disabled, differ- ential input buffers will be shut off, ...
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Serializer Operation Mode FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE) FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE) FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) (Continued) 5 Preliminary www.fairchildsemi.com ...
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Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct ...
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... LVDS by sourcing and sinking a balanced current through the output pair. Like LVDS an input source termination resistor is required to develop a voltage at the differential input pair. The FIN12A device incorporates an internal ter- mination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated ter- mination resistor insures proper termination regardless of direction of data flow ...
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PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL will generate internal timing signals capable of transferring data at 14 times the incoming CKREF signal. The output of the PLL is a ...
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Application Mode Diagrams Modes Unidirectional Data Transfer FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 8 shows the basic operation diagram when a pair of SerDes is configured in an unidirectional operation mode. Master ...
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... Figure 11 shows an application for a camera interface for a flip phone using the FIN12A. For this application the refer- www.fairchildsemi.com (Continued) ence clock is generated on the baseband side of the flip and passed across the SerDes pair differentially ...
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Absolute Maximum Ratings Supply Voltage ( ALL Input/Output Voltage LVDS Output Short Circuit Duration Storage Temperature Range (T ) STG Maximum Junction Temperature ( Lead Temperature ( (Soldering, 4 seconds) ESD Rating Human Body ...
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Power Supply Currents Symbol Parameter I V Serializer Static All DP and Control Inputs DDA1 DDA Supply Current NOCKREF Deserializer Static All DP and Control Inputs DDA2 DDA Supply ...
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Serializer AC Electrical Characteristics Serializer Timing Characteristics Symbol Parameter t Differential Output Rise Time (20% to 80%) TLH t Differential Output Fall Time (80% to 20%) THL t DP[n] Setup to STROBE STC t DP[n] Hold to STROBE HTC t ...
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Control Logic Timing Controls Symbol Parameter t , Propagation Delay PHL_DIR DIRI LOW-to-HIGH or HIGH-to-LOW t DIRI-to-DIRO PLH_DIR t , Propagation Delay PLZ DIRI LOW-to-HIGH t DIRI-to-DP PHZ t , Propagation Delay PZL DIRI HIGH-to-LOW t DIRI-to-DP PZH t , ...
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AC Loading and Waveforms FIGURE 12. Differential LpLVDS Output DC Test Circuit FIGURE 14. “Worst Case” Serializer Test Pattern FIGURE 15. LpLVDS Output Load and Transition Times Note A: For All input pulses ...
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AC Loading and Waveforms Setup: Mode0 “0” or “1”m MODE1 “1”, SER/DES FIGURE 17. Serial Setup and Hold Time Setup: DIRI “0”, CKSI and DS are Valid Signals FIGURE 19. Deserializer Data Valid Window Time and Clock Output Parameters Note: ...
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AC Loading and Waveforms FIGURE 23. Differential Input Setup and Hold Times Note: CKREF Signal can be stopped either HIGH or LOW FIGURE 25. PLL Loss of Clock Disable Time Note: CKREF must be active and PLL must be stable ...
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Tape and Reel Specification TAPE FORMAT for USS-BGA Dimensions are in millimeters Package 0.10 0.10 0.05 min 3.5 x 4.5 TBD TBD 1.55 1.5 Note: A0, B0, and K0 dimensions are determined with ...
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Tape and Reel Specification TAPE FORMAT for MLP Package Tape Designator Section Leader (Start End) MLX Carrier Trailer (Hub End) MLP Embossed Tape Dimension (Continued) Number Cavity Cavities Status 125 (typ) Empty 2500/3000 Filled 75 (typ) Empty 19 Preliminary Cover ...
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Physical Dimensions inches (millimeters) unless otherwise noted Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide www.fairchildsemi.com Package Number BGA042A 20 Preliminary ...
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Physical Dimensions Physical Dimensions inches (millimeters) unless otherwise noted (Continued) inches (millimeters) unless otherwise noted (Continued) Pb-Free 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square Fairchild does not assume any responsibility for use of any circuitry described, no ...