fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 96

• Manufacturer Part Number: fdc37m707
• Description: Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
• Manufacturer: Standard Microsystems Corp.

R/W
000:
001:
010:
011:
100:
101:
110:
111:
IRQ SELECTED
All Others
Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers
are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction
bit will not tri-state the output drivers in this mode.
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the
value in the data register. All drivers have active pull-ups (push-pull).
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to
the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol.
Note that this mode is only useful when direction is 0. All drivers have active pull-ups
(push-pull).
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the
ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted
automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1)
bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All
drivers have active pull-ups (push-pull).
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register L3-CRF0. All drivers have active pull-ups (push-pull).
Reserved
Test Mode. In this mode the FIFO may be written and read, but the data will not be
transmitted on the parallel port. All drivers have active pull-ups (push-pull).
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (push-pull).
data lines and reading the data register returns the value on the data lines and not the
15
14
11
10
9
7
5
Table 39B
CONFIG REG B
Table 39A - Extended Control Register
BITS 5:3
110
101
100
011
010
001
111
000
96
MODE
DMA SELECTED
All Others
Table 39C
3
2
1
CONFIG REG B
BITS 2:0
011
010
001
000