fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 135

• Manufacturer Part Number: fdc37m707
• Description: Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
• Manufacturer: Standard Microsystems Corp.

Card Level
Reserved
Device ID
Hard wired
= 0x42
Device Rev
Hard wired
= Current Revision
PowerControl
Default = 0x00.
on Vcc POR or
Reset_Drv hardware
signal
Power Mgmt
Default = 0x00.
on Vcc POR or
Reset_Drv hardware
signal
REGISTER
0x08 - 0x1F Reserved - Writes are ignored, reads return 0.
ADDRESS
0x22 R/W
0x23 R/W
0x20 R
0x21 R
Table 53 - Chip Level Registers
Chip Level, SMSC Defined
A read only register which provides device
identification. Bits[7:0] = 0x42 when read.
A read only register which provides device revision
information. Bits[7:0] = current revision when read.
Bit[0] FDC Power
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6] Reserved
Bit[7] Reserved
Bit[0] FDC
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6:7] Reserved (read as 0)
= 0
= 1
Intelligent Pwr Mgmt off
Intelligent Pwr Mgmt on
135
DESCRIPTION
STATE
C
C
C
C