fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 88

• Manufacturer Part Number: fdc37m707
• Description: Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
• Manufacturer: Standard Microsystems Corp.

Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
PDIR
SIGNAL
EPP
cycle. For correct EPP read cycles, PCD is required to be a low.
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
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Selected
Status
Error
Parallel Port
Direction
EPP NAME
TYPE
I/O
Table 35 - EPP Pin Descriptions
O
O
O
O
O
I
I
I
I
I
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low.
acknowledgement from the device that the transfer of data is
completed.
device is ready for the next transfer.
This signal is active low.
write operation.
This signal is active low.
device is reset to its initial operational mode.
This signal is active low. It is used to denote address read
or write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
This output shows the direction of the data transfer on the
parallel port bus. A low means an output/write condition and
a high means an input/read condition.
normally a low (output/write) unless PCD of the control
register is set or if an EPP read cycle is in progress.
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It is driven active as an indication that the
EPP DESCRIPTION
It is used to denote data read or
It is driven inactive as a positive
When driven active, the EPP
This signal is