fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 121

• Manufacturer Part Number: fdc37m707
• Description: Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
• Manufacturer: Standard Microsystems Corp.

EXTERNAL
INTERFACE
Industry-standard PC-AT-compatible keyboards
employ a two-wire, bidirectional TTL interface
for data transmission.
supply PS/2 mouse products that employ the
same type of interface.
expansion, the FDC37M70x provides four signal
pins that may be used to implement this
interface directly for an external keyboard and
mouse.
The FDC37M70x has four high-drive, open-drain
output, bidirectional port pins that can be used
for external serial interfaces, such as ISA
external
interfaces. They are KCLK, KDAT, MCLK, and
MDAT. P26 is inverted and output as KCLK. The
KCLK pin is connected to TEST0.
inverted and output as KDAT. The KDAT pin is
connected to P10. P23 is inverted and output as
MCLK. The MCLK pin is connected to TEST1.
P22 is inverted and output as MDAT. The MDAT
pin is connected to P11. NOTE: External pull-
ups may be required.
KEYBOARD POWER MANAGEMENT
The keyboard provides support for two power-
saving modes: soft powerdown mode and hard
powerdown mode.
the clock to the ALU is stopped but the
timer/counter and interrupts are still active. In
hard power down mode the clock to the 8042 is
stopped.
Soft Power Down Mode
This mode is entered by executing a HALT
instruction. The execution of program code is
halted until either RESET is driven active or a
data byte is written to the DBBIN register by a
master CPU. If this mode is exited using the
interrupt, and the IBF interrupt is enabled, then
program execution resumes with a CALL to the
keyboard
KEYBOARD
In soft powerdown mode,
and
Several sources also
To facilitate system
PS/2-type
AND
MOUSE
P27 is
mouse
121
interrupt routine, otherwise the next instruction
is executed. If it is exited using RESET then a
normal reset sequence is initiated and program
execution starts from program memory location
0.
Hard Power Down Mode
This mode is entered by executing a STOP
instruction.
disabling the
either RESET is driven active or a data byte is
written to the DBBIN register by a master CPU,
this mode will be exited (as above). However,
as the oscillator cell will require an initialization
time, either RESET must be held active for
sufficient time to allow the oscillator to stabilize.
INTERRUPTS
The
interrupts. IBF and the Timer/Counter Overflow.
MEMORY CONFIGURATIONS
The FDC37M70x provides 2K of on-chip ROM
and 256 bytes of on-chip RAM.
Register Definitions
Host I/F Data Register
The Input Data register and Output Data register
are each 8 bits wide. A write to this 8 bit register
will load the Keyboard Data Read Buffer, set the
OBF flag and set the KIRQ output if enabled. A
read of this register will read the data from the
Keyboard Data or Command Write Buffer and
clear the IBF flag. Refer to the KIRQ and Status
register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide.
shows the contents of the Status register.
Program execution will resume as above.
FDC37M70x
The oscillator is stopped by
oscillator
provides
driver
the
cell.
two
Table 50
When
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