fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 170
![no-image](/images/no-image-200.jpg)
fdc37m707
Manufacturer Part Number
fdc37m707
Description
Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
Manufacturer
Standard Microsystems Corp.
Datasheet
1.FDC37M707.pdf
(194 pages)
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Note:
Note:
CLOCKI
RESET_DRV
NAME
NAME
t1
t2
t4
Tolerance is
The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
Clock Cycle Time for 14.318MHz (Note)
Clock High Time/Low Time for 14.318MHz
Clock Rise Time/Fall Time (not shown)
RESET width (Note)
0.01%
DESCRIPTION
DESCRIPTION
FIGURE 7A - INPUT CLOCK TIMING
FIGURE 7B - RESET TIMING
t1
170
t4
t2
MIN
20
MIN
1.5
69.84
TYP
t2
TYP
35
MAX
MAX
5
UNITS
UNITS
ns
ns
ns
s
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