isp1582 NXP Semiconductors, isp1582 Datasheet - Page 57

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isp1582

Manufacturer Part Number
isp1582
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
ISP1582_6
Product data sheet
Fig 18. GDMA mode timing (bits MODE[1:0] = 01)
Fig 19. GDMA mode timing (bits MODE[1:0] = 10)
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
(write) DATA [ 15:0 ]
(read) DATA [ 15:0 ]
(write) DATA [ 15:0 ]
(read) DATA [ 15:0 ]
DIOR or DIOW
DIOR or DIOW
DREQ is asserted for every transfer.
Data strobes: DIOR (read) and DACK (write).
DREQ is continuously asserted, until the last transfer is done or the FIFO is full.
Data strobe: DACK (read/write).
DREQ
DACK
DREQ
DACK
(2)
(1)
(1)
(2)
(1)
(1)
HIGH
t
su1
t
su1
t
su3
t
t
d2
d2
t
w1
t
t
w1
su2
t
su2
Rev. 06 — 20 September 2007
t
h2
t
h2
t
t
w2
h3
t
h3
T
T
cy1
cy1
Hi-Speed USB Peripheral Controller
t
d1
t
h1
t
h1
© NXP B.V. 2007. All rights reserved.
t
d1
ISP1582
t
a1
mgt502
mgt501
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