isp1582 NXP Semiconductors, isp1582 Datasheet - Page 42

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 52.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Reason register: bit allocation
8.4.5 DMA Interrupt Reason register (address: 50h)
TEST3
15
R
7
-
-
-
-
-
Table 51.
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a
DMA command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. On detecting the interrupt, the external microprocessor must read the
DMA Interrupt Reason register and mask it with the corresponding bits in the DMA
Interrupt Enable register to determine the source of the interrupt.
The bit allocation is given in
Table 53.
Bit
3
2
1
0
Bit
15
14 to 13 -
12
14
Symbol
ACK_POL
DREQ_POL
WRITE_POL
READ_POL
6
-
-
-
-
-
-
Symbol
TEST3
GDMA_STOP
reserved
DMA Hardware register: bit description
DMA Interrupt Reason register: bit description
13
5
-
-
-
-
-
-
Rev. 06 — 20 September 2007
Description
Acknowledgment Polarity: Selects the DMA acknowledgment polarity.
0 — DACK is active LOW
1 — DACK is active HIGH
DREQ Polarity: Selects the DMA request polarity.
0 — DREQ is active LOW
1 — DREQ is active HIGH
Write Polarity: Selects the DIOW strobe polarity.
0 — DIOW is active LOW
1 — DIOW is active HIGH
Read Polarity: Selects the DIOR strobe polarity.
0 — DIOR is active LOW
1 — DIOR is active HIGH
Description
This bit is set when the DMA transfer for a packet (OUT transfer)
terminates before the whole packet has been transferred. This bit is a
status bit, and the corresponding mask bit of this register is always
logic 0. Writing any value other than logic 0 has no effect.
reserved
GDMA Stop: When the GDMA_STOP command is issued to DMA
Command registers, it means the DMA transfer has successfully
terminated.
Table
GDMA_
STOP
R/W
12
0
0
4
-
-
-
52.
reserved
EXT_EOT
R/W
11
0
0
3
-
-
-
…continued
Hi-Speed USB Peripheral Controller
INT_EOT
R/W
10
0
0
2
-
-
-
reserved
R/W
9
1
-
-
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1582
XFER_OK
DMA_
R/W
8
0
0
0
-
-
-
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