isp1582 NXP Semiconductors, isp1582 Datasheet - Page 26

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 20.
Table 23.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt Configuration register: bit allocation
OTG register: bit allocation
8.2.4 OTG register (address: 12h)
R/W
7
CDBGMOD[1:0]
-
-
-
7
1
1
reserved
CDBGMOD[1:0] — Interrupts for control endpoint 0
DDBGMODIN[1:0] — Interrupts for DATA IN endpoints 1 to 7
DDBGMODOUT[1:0] — Interrupts for DATA OUT endpoints 1 to 7
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you
to individually configure when the ISP1582 sends an interrupt to the external
microprocessor.
Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or
falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to
logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
Table 21.
Table 22.
[1]
The bit allocation of the OTG register is given in
Bit
7 to 6
5 to 4
3 to 2
1
0
Value
00h
01h
1Xh
First NAK: the first NAK on an IN or OUT token is generated after a set-up token and an ACK sequence.
6
R/W
-
-
-
6
1
1
CDBGMOD
interrupt on all ACK and
NAK
interrupt on all ACK
interrupt on all ACK and
first NAK
Symbol
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see
INTLVL
INTPOL
Interrupt Configuration register: bit description
Debug mode settings
[1]
Table 22
R/W
DP
5
0
0
DDBGMODIN[1:0]
R/W
5
1
1
Rev. 06 — 20 September 2007
BSESSVALID
lists the available combinations.
R/W
Description
Control Endpoint 0 Debug Mode: For values, see
Data Debug Mode IN: For values, see
Interrupt Level: Selects signaling mode on output INT (0 = level;
1 = pulsed). In pulsed mode, an interrupt produces a 60 ns pulse.
Interrupt Polarity: Selects signal polarity on output INT (0 =
active LOW; 1 = active HIGH).
4
-
-
R/W
4
1
1
DDBGMODIN
interrupt on all ACK and
NAK
interrupt on ACK
interrupt on all ACK and
first NAK
INITCOND
DDBGMODOUT[1:0]
[1]
R/W
R/W
3
-
-
3
1
1
Table
Hi-Speed USB Peripheral Controller
23.
DISCV
R/W
R/W
2
0
0
2
1
1
DDBGMODOUT
interrupt on all ACK, NYET and
NAK
interrupt on ACK and NYET
interrupt on all ACK, NYET and
first NAK
Table 22
unchanged
INTLVL
Table 22
[1]
R/W
R/W
VP
1
0
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1582
Table 22
unchanged
INTPOL
OTG
R/W
R/W
0
0
0
0
0
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