isp1582 NXP Semiconductors, isp1582 Datasheet - Page 39

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 45.
Table 46.
ISP1582_6
Product data sheet
Code
0Fh
10h
11h
12h
13h
14h to FFh
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
DMA commands
DMA Transfer Counter register: bit allocation
Name
Clear Buffer
-
Reset DMA
-
GDMA Stop
-
8.4.2 DMA Transfer Counter register (address: 34h)
R/W
R/W
31
23
15
0
0
0
0
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in
For IN endpoint — Because there is a FIFO in the ISP1582 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is
read from the DMA FIFO.
If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when
it reaches zero.
Description
Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a
DMA-to-USB data transfer. Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer
is not affected. The TX buffer is automatically cleared once data is sent on the USB bus. This
bit is set only when it is necessary to forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the Clear Buffer command two
times, that is, set and clear this bit two times.
reserved
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK,
DIOW and DIOR handshake pins will temporarily be asserted. This can confuse the external
DMA controller. To prevent this, start the external DMA controller only after the DMA reset.
reserved
GDMA stop: This command stops the GDMA data transfer. Any data in the OUT endpoint
that is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint
will be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of
the DMA Stop command.
reserved
…continued
R/W
R/W
30
22
14
0
0
0
0
R/W
R/W
Rev. 06 — 20 September 2007
29
21
13
0
0
0
0
DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
DMACR2 = DMACR[15:8]
R/W
R/W
28
20
12
0
0
0
0
R/W
R/W
27
19
11
0
0
0
0
Hi-Speed USB Peripheral Controller
R/W
R/W
26
18
10
0
0
0
0
R/W
R/W
25
17
0
0
0
0
9
© NXP B.V. 2007. All rights reserved.
ISP1582
Table
46.
R/W
R/W
24
16
0
0
0
0
8
39 of 69