isp1582 NXP Semiconductors, isp1582 Datasheet - Page 54

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isp1582

Manufacturer Part Number
isp1582
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 80.
V
ISP1582_6
Product data sheet
Symbol
Reading
t
t
t
t
t
t
t
Writing
t
t
t
t
t
t
RLRH
AVRL
RHAX
RLDV
RHDZ
RHSH
SLRL
WLWH
AVWL
WHAX
DVWH
WHDZ
WHSH
Fig 14. Receiver differential data jitter
CC(I/O)
differential
data lines
= V
T
PERIOD
Parameter
RD_N LOW pulse width
address set-up time before RD_N LOW
address hold time after RD_N HIGH
RD_N LOW to data valid delay
RD_N HIGH to data outputs 3-state delay
RD_N HIGH to CS_N HIGH delay
CS_N LOW to RD_N LOW delay
WR_N LOW pulse width
address set-up time before WR_N LOW
address hold time after WR_N HIGH
data set-up time before WR_N HIGH
data hold time after WR_N HIGH
WR_N HIGH to CS_N HIGH delay
3.3 V
Register access timing parameters: separate address and data buses
CC
0 V
= 3.3 V; V
12.1 Register access timing
is the bit duration corresponding to the USB data rate.
T
PERIOD
GND
Fig 15. Receiver SE0 width tolerance
= 0 V; T
t
JR
amb
N
= 40 C to +85 C.
consecutive
T
transitions
PERIOD
Rev. 06 — 20 September 2007
t
JR1
differential
data lines
N
Conditions
3.3 V
T
transitions
0 V
PERIOD
paired
t
JR2
Min
> t
0
0
-
0
0
2
15
0
0
11
5
0
t
JR1
RLDV
Hi-Speed USB Peripheral Controller
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
t
FST
V
IH(min)
mgr872
Max
-
-
-
26
15
-
-
-
-
-
-
-
-
t
JR2
© NXP B.V. 2007. All rights reserved.
ISP1582
mgr871
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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