isp1582 NXP Semiconductors, isp1582 Datasheet - Page 45

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 60.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt register: bit allocation
8.5.1 Interrupt register (address: 18h)
EP6TX
EP2TX
VBUS
R/W
R/W
R/W
8.5 General registers
31
23
15
0
0
0
0
7
0
0
-
-
-
The Interrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the Interrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the Interrupt register content is nonzero, the INT output will
be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the
external microprocessor must read the Interrupt register and mask it with the
corresponding bits in the Interrupt Enable register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register.
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.
Table 61.
Bit
31 to 26
25
24
EP6RX
EP2RX
DMA
R/W
R/W
R/W
30
22
14
0
0
0
0
6
0
0
-
-
-
Interrupt register: bit description
Symbol
-
EP7TX
EP7RX
HS_STAT
EP5TX
EP1TX
R/W
R/W
R/W
29
21
13
0
0
0
0
5
0
0
-
-
-
Rev. 06 — 20 September 2007
reserved
Description
reserved
logic 1 indicates the endpoint 7 TX buffer as interrupt source
logic 1 indicates the endpoint 7 RX buffer as interrupt source
RESUME
EP5RX
EP1RX
R/W
R/W
R/W
28
20
12
0
0
0
0
4
0
0
-
-
-
EP4TX
EP0TX
SUSP
R/W
R/W
R/W
27
19
11
0
0
0
0
3
0
0
-
-
-
Hi-Speed USB Peripheral Controller
EP4RX
EP0RX
PSOF
R/W
R/W
R/W
26
18
10
0
0
0
0
2
0
0
-
-
-
reserved
EP7TX
EP3TX
SOF
R/W
R/W
R/W
25
17
9
Table
0
0
0
0
1
0
0
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1582
60.
EP0SETUP
BRESET
EP7RX
EP3RX
R/W
R/W
R/W
R/W
24
16
8
0
0
0
0
0
0
0
0
1
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