isp1582 NXP Semiconductors, isp1582 Datasheet - Page 10

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1582_6
Product data sheet
7.6.3 HS detection
7.6.4 Isolation
7.7 NXP Serial Interface Engine (SIE)
7.8 SoftConnect
7.9 Clear buffer
The ISP1582 handles more than one electrical state, Full-Speed (FS) or High-Speed
(HS), under the USB specification. When the USB cable is connected from the peripheral
to the Host Controller, the ISP1582 defaults to the FS state, until it sees a bus reset from
the Host Controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the Host
Controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there
is an HS host connected, then the ISP1582 switches to the HS state.
In the HS state, the ISP1582 must observe the bus for periodic activity. If the bus remains
inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero
(SE0) condition on the USB bus. If an SE0 condition is detected for the designated time
(100 s to 875 s; refer to
Section 7.1.7.6), the ISP1582 switches to the HS chirp state to perform an HS detection
handshake. Otherwise, the ISP1582 remains in the FS state, adhering to the bus-suspend
specification.
Ensure that the DP and DM lines are maintained in a clean state, without any residual
voltage or glitches. Once the ISP1582 is reset and the clock is available, ensure that there
are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines.
Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1582
DP and DM lines, there is a possibility of the ISP1582 clocking this state into the internal
core, causing unknown behaviors.
The NXP SIE implements the full USB protocol layer. It is completely hardwired for speed
and needs no firmware intervention. The functions of this block include: synchronization
pattern recognition, parallel or serial conversion, bit-stuffing or de-stuffing, CRC checking
or generation, Packet IDentifier (PID) verification or generation, address recognition,
handshake evaluation or generation.
The USB connection is established by pulling pin DP (for full-speed devices) to HIGH
through a 1.5 k pull-up resistor. In the ISP1582, an external 1.5 k pull-up resistor must
be connected between pin RPU and 3.3 V. Pin RPU connects the pull-up resistor to pin
DP, when bit SOFTCT in the Mode register is set (see
hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0). The USB
bus reset does not change the value of bit SOFTCT.
When V
back-drive voltage.
Use clear buffer when data needs to be discarded under the following conditions:
BUS
is not present, the SOFTCT bit must be set to logic 0 to comply with the
Rev. 06 — 20 September 2007
Ref. 1 “Universal Serial Bus Specification Rev.
Hi-Speed USB Peripheral Controller
Table 17
and
Table
© NXP B.V. 2007. All rights reserved.
ISP1582
2.0”,
18). After a
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