isp1563 NXP Semiconductors, isp1563 Datasheet - Page 97

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. REVID - Revision ID register (address 08h)
Table 11. CC - Class Code register (address 09h)
Table 12. CC - Class Code register (address 09h)
Table 13. CLS - CacheLine Size register (address 0Ch)
Table 14. LT - Latency Timer register (address 0Dh)
Table 15. HT - Header Type register (address 0Eh)
Table 16. HT - Header Type register (address 0Eh)
Table 17. BAR0 - Base Address register 0
Table 18. SVID - Subsystem Vendor ID register
Table 19. SID - Subsystem ID register (address 2Eh)
Table 20. CP - Capabilities Pointer register
Table 21. IL - Interrupt Line register (address 3Ch)
Table 22. IP - Interrupt Pin register (address 3Dh)
Table 23. MIN_GNT - Minimum Grant register
Table 24. MAX_LAT - Maximum Latency register
Table 25. EHCI-specific PCI registers . . . . . . . . . . . . . . .25
Table 26. SBRN - Serial Bus Release Number register
ISP1563_2
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
PCI configuration space registers of
OHCI1, OHCI2 and EHCI . . . . . . . . . . . . . . . .16
VID - Vendor ID register (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
DID - Device ID register (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
CMD - Command register (address 04h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .17
CMD - Command register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .18
STATUS - Status register (address 06h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
STATUS - Status register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .19
bit description . . . . . . . . . . . . . . . . . . . . . . . . .20
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .20
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
(address 10h) bit description . . . . . . . . . . . . . .22
(address 2Ch) bit description . . . . . . . . . . . . . .22
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
(address 34h) bit description . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
(address 3Eh) bit description . . . . . . . . . . . . . .24
(address 3Fh) bit description . . . . . . . . . . . . . .24
Rev. 02 — 15 March 2007
Table 27. FLADJ - Frame Length Adjustment register
Table 28. FLADJ - Frame Length Adjustment register
Table 29. FLADJ value as a function of SOF
Table 30. PORTWAKECAP - Port Wake Capability
Table 31. Power Management registers . . . . . . . . . . . . . 26
Table 32. CAP_ID - Capability Identifier register
Table 33. NEXT_ITEM_PTR - Next Item Pointer
Table 34. PMC - Power Management Capabilities
Table 35. PMC - Power Management Capabilities
Table 36. PMCSR - Power Management
Table 37. PMCSR - Power Management
Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 40. PCI bus power and clock control . . . . . . . . . . . 30
Table 41. DATA - Data register bit description . . . . . . . . . 31
Table 42. USB Host Controller registers . . . . . . . . . . . . . 34
Table 43. HcRevision - Host Controller Revision
Table 44. HcRevision - Host Controller Revision
Table 45. HcControl - Host Controller Control
Table 46. HcControl - Host Controller Control
Table 47. HcCommandStatus - Host Controller
Table 48. HcCommandStatus - Host Controller
Table 49. HcInterruptStatus - Host Controller
Table 50. HcInterruptStatus - Host Controller
Table 51. HcInterruptEnable - Host Controller
Table 52. HcInterruptEnable - Host Controller
(address 60h) bit description . . . . . . . . . . . . . . 25
(address 61h) bit allocation . . . . . . . . . . . . . . . 25
(address 61h) bit description . . . . . . . . . . . . . . 25
cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
register (address 62h) bit description . . . . . . . 26
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 27
register bit description . . . . . . . . . . . . . . . . . . . 27
register bit allocation . . . . . . . . . . . . . . . . . . . . 27
register bit description . . . . . . . . . . . . . . . . . . . 28
Control/Status register bit allocation . . . . . . . . 29
Control/Status register bit description . . . . . . . 29
Support Extensions register bit allocation . . . . 30
Support Extensions register bit description . . . 30
register bit allocation . . . . . . . . . . . . . . . . . . . . 36
register bit description . . . . . . . . . . . . . . . . . . . 37
register bit allocation . . . . . . . . . . . . . . . . . . . . 37
register bit description . . . . . . . . . . . . . . . . . . . 37
Command Status register bit allocation . . . . . 39
Command Status register bit description . . . . 40
Interrupt Status register bit allocation . . . . . . . 40
Interrupt Status register bit description . . . . . . 41
Interrupt Enable register bit allocation . . . . . . . 42
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1563
continued >>
97 of 102