isp1563 NXP Semiconductors, isp1563 Datasheet - Page 73

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 106. USBSTS - USB Status register bit description
Address: Content of the base address register + 24h
Table 107. USBINTR - USB Interrupt Enable register bit allocation
Address: Content of the base address register + 28h
[1]
Table 108. USBINTR - USB Interrupt Enable register bit description
Address: Content of the base address register + 28h
ISP1563_2
Product data sheet
Bit
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 6
5
4
The reserved bits should always be written with the reset value.
Symbol
reserved
IAAE
HSEE
Symbol
USBINT
11.4.3 USBINTR register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
Description
-
Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS
register) are set, the Host Controller issues an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software clearing bit IAA.
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the Host
Controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE.
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in the USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is given in
Description
USB Interrupt: The Host Controller sets this bit on completing a USB transaction, which results
in the retirement of a TD that had its IOC bit set. The Host Controller also sets this bit when a
short packet is detected, that is, the actual number of bytes received was less than the expected
number of bytes. For details, refer to Enhanced Host Controller Interface Specification for
Universal Serial Bus Rev. 1.0 .
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
IAAE
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 02 — 15 March 2007
HSEE
R/W
R/W
R/W
R/W
Table
28
20
12
…continued
0
0
0
4
0
reserved
reserved
reserved
107.
[1]
[1]
[1]
FLRE
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
PCIE
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
USBERR
INTE
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
USBINTE
R/W
R/W
R/W
R/W
73 of 102
24
16
0
0
8
0
0
0