isp1563 NXP Semiconductors, isp1563 Datasheet - Page 42

no-image

isp1563

Manufacturer Part Number
isp1563
Description
Hi-speed Universal Serial Bus Pci Host Controller
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
isp1563BM
Manufacturer:
BROADCOM
Quantity:
9 240
Company:
Part Number:
isp1563BM
Quantity:
5
Part Number:
isp1563BMGA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
isp1563BMGE
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
isp1563BMUM
Manufacturer:
NXP
Quantity:
670
Part Number:
isp1563BMUM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 51.
[1]
Table 52.
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30
29 to 7
6
5
Address: Content of the base address register + 10h
Address: Content of the base address register + 10h
The reserved bits should always be written with the reset value.
Symbol
MIE
OC
reserved
RHSC
FNO
HcInterruptEnable - Host Controller Interrupt Enable register bit allocation
HcInterruptEnable - Host Controller Interrupt Enable register bit description
reserved
R/W
R/W
R/W
R/W
MIE
31
23
15
0
0
0
7
0
[1]
Description
Master Interrupt Enable:
0 — Ignore
1 — Enables interrupt generation by events specified in other bits of this register.
Ownership Change:
0 — Ignore
1 — Enables interrupt generation because of ownership change.
-
Root Hub Status Change:
0 — Ignore
1 — Enables interrupt generation because of root hub status change.
Frame Number Overflow:
0 — Ignore
1 — Enables interrupt generation because of frame number overflow.
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to
a bit in this register leaves the corresponding bit unchanged. On a read, the current value
of this register is returned. The bit allocation is given in
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (Master Interrupt Enable) bit is set.
RHSC
R/W
R/W
R/W
R/W
OC
30
22
14
0
0
0
6
0
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 02 — 15 March 2007
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
reserved
[1]
Table
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
51.
WDH
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
R/W
R/W
R/W
R/W
SO
42 of 102
24
16
0
0
8
0
0
0

Related parts for isp1563