isp1563 NXP Semiconductors, isp1563 Datasheet - Page 74

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 108. USBINTR - USB Interrupt Enable register bit description
Address: Content of the base address register + 28h
Table 109. FRINDEX - Frame Index register bit allocation
Address: Content of the base address register + 2Ch
[1]
ISP1563_2
Product data sheet
Bit
3
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
FLRE
PCIE
USBERR
INTE
USBINTE
11.4.4 FRINDEX register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
Description
Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the Host
Controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR.
Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the
Host Controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD.
USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set,
the Host Controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged
by software clearing bit USBERRINT.
USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the Host
Controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing bit USBINT.
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125 s; once each microframe. Bits N to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in FLS[1:0] (bits 3 to 2) of the USBCMD register. This register
must be written as a DWORD. Byte writes produce undefined results. This register cannot
be written unless the Host Controller is in the halted state, as indicated by HCH (bit 12 in
the USBSTS register). A write to this register while RS (bit 0 in the USBCMD register) is
set produces undefined results. Writes to this register also affect the SOF value.
The bit allocation is given in
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 02 — 15 March 2007
Table
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
FRINDEX[7:0]
109.
reserved
reserved
[1]
[1]
…continued
R/W
R/W
R/W
R/W
27
19
11
FRINDEX[13:8]
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
R/W
R/W
R/W
R/W
74 of 102
24
16
0
0
8
0
0
0