isp1563 NXP Semiconductors, isp1563 Datasheet - Page 49

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 66.
Address: Content of the base address register + 2Ch
Table 67.
Address: Content of the base address register + 30h
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
BCED[27:0]
reserved
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description
HcDoneHead - Host Controller Done Head register bit allocation
11.1.13 HcDoneHead register
R/W
R/W
R/W
R/W
R/W
15
31
23
15
0
7
0
0
0
0
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
of the register.
Description
Bulk Current ED: This is advanced to the next ED after the Host Controller has served the
current ED. The Host Controller continues processing the list from where it left off in the last
frame. When it reaches the end of the bulk list, the Host Controller checks CLF (bit 1 of
HcCommandStatus). If the CLF bit is not set, nothing is done. If the CLF bit is set, it copies the
content of HcBulkHeadED to HcBulkCurrentED and clears the CLF bit. The HCD can modify this
register only when BLE (bit 5 in the HcControl register) is cleared. When HcControl is set, the
HCD reads the instantaneous value of this register. This is initially set to logic 0 to indicate the end
of the bulk list.
-
R/W
R/W
R/W
R/W
R/W
14
30
22
14
0
6
0
0
0
0
BCED[3:0]
R/W
R/W
R/W
R/W
R/W
13
29
21
13
0
5
0
0
0
0
Rev. 02 — 15 March 2007
R/W
R/W
R/W
R/W
R/W
12
28
20
12
0
4
0
0
0
0
BCED[11:4]
DH[27:20]
DH[19:12]
DH[11:4]
R/W
R/W
R/W
R/W
R/W
11
27
19
11
0
3
0
0
0
0
Table 67
R/W
R/W
R/W
R/W
R/W
10
26
18
10
0
2
0
0
0
0
HS USB PCI Host Controller
reserved
contains the bit allocation
[1]
R/W
R/W
R/W
R/W
R/W
25
17
9
0
1
0
0
0
9
0
© NXP B.V. 2007. All rights reserved.
ISP1563
R/W
R/W
R/W
R/W
R/W
49 of 102
24
16
8
0
0
0
0
0
8
0