dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 66

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

4.0 Register Set
4.2.31 Receive Descriptor Pointer 1 Register
This register points to the Receive Descriptor for Priority Queue 1.
4.2.32 Receive Descriptor Pointer 2 Register
This register points to the Receive Descriptor for Priority Queue 2.
31-3
31-3
2-0
2-0
bit
bit
RXDP1
RXDP2
tag
tag
Offset: 00B0h
Offset: 00B4h
Receive
Descriptor Pointer
1
Receive
Descriptor Pointer
2
(Continued)
Tag: RXDP1
Tag: RXDP2
description
description
The current value of the receive descriptor pointer for Priority Queue 1. Packets will be
stored in Priority Queue 1 based on the number of priority queues enabled and the
priority field in the VLAN tag. When the receive state machine is idle, software must set
RXDP1 to the address of an available receive descriptor, and then enable the queue by
writing to the RXE bit in the CR with the RXPRI[1] bit set. While the receive state machine
is active, RXDP1 will follow the state machine as it advances through a linked list of
available descriptors. If the link field of the current receive descriptor is NULL (signifying
the end of the list), RXDP1 will not advance, but will remain on the current descriptor. Any
subsequent writes to the RXE bit of the CR register will cause the receive state machine
to reread the link field of the current descriptor to check for new descriptors that may have
been appended to the end of the list. Software should not write to this register unless the
receive state machine is idle. Receive descriptors must be aligned on 64-bit boundaries
(A2-A0 must be zero).
unused
The current value of the receive descriptor pointer for Priority Queue 2. Packets will be
stored in Priority Queue 2 based on the number of priority queues enabled and the
priority field in the VLAN tag. When the receive state machine is idle, software must set
RXDP2 to the address of an available receive descriptor, and then enable the queue by
writing to the RXE bit in the CR with the RXPRI[2] bit set. While the receive state machine
is active, RXDP2 will follow the state machine as it advances through a linked list of
available descriptors. If the link field of the current receive descriptor is NULL (signifying
the end of the list), RXDP2 will not advance, but will remain on the current descriptor. Any
subsequent writes to the RXE bit of the CR register will cause the receive state machine
to reread the link field of the current descriptor to check for new descriptors that may have
been appended to the end of the list. Software should not write to this register unless the
receive state machine is idle. Receive descriptors must be aligned on 64-bit boundaries
(A2-A0 must be zero).
unused
Access: Read Write
Access: Read Write
Size: 32 bits
Size: 32 bits
66
usage
usage
Hard Reset: 00000000h
Hard Reset: 00000000h
Soft Reset: 00000000h
Soft Reset: 00000000h
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