dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 3

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

2.0 Pin Descriptions
PCI Interface
AD31-0
CBEN3-0
PCICLK
DEVSELN
FRAMEN
GNTN
IDSEL
INTAN
IRDYN
PAR
PERRN
REQN
RSTN
Symbol
188, 189, 190,
191, 192, 193,
194, 195, 199,
200, 202, 203,
204, 207, 208,
18, 19, 21, 22,
23, 25, 26, 28,
29, 31, 32, 33,
197, 2, 13, 24
1, 14, 15, 17,
Pin No(s)
176
185
198
183
186
184
34
12
10
8
4
5
Direction
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
Address and Data: Multiplexed address and data bus. As a bus master, the
DP83820 will drive address during the first bus phase. During subsequent
phases, the DP83820 will either read or write data expecting the target to
increment its address pointer. As a bus target, the DP83820 will decode each
address on the bus and respond if it is the target being addressed.
Bus Command/Byte Enable: During the address phase these signals define
the “bus command” or the type of bus transaction that will take place. During the
data phase these pins indicate which byte lanes contain valid data. CBEN0
applies to byte 0 (bits 7-0) and CBEN3 applies to byte 3(bits 31-24).
Clock: This PCI Bus clock provides timing for all bus phases. The rising edge
defines the start of each phase. The clock frequency ranges from 0 to 66 MHz.
Device Select: As a target, the DP83820 asserts this signal low when it
recognizes its address after FRAMEN is asserted. As a bus master, the
DP83820 samples this signal to insure that the destination address for the data
transfer is recognized by a PCI target.
Frame: As a bus master, this signal is asserted low to indicate the beginning
and duration of a bus transaction. Data transfer takes place when this signal is
asserted. It is de-asserted before the transaction is in its final phase. As a
target, the device monitors this signal before decoding the address to check if
the current transaction is addressed to it.
Grant: This signal is asserted low to indicate to the DP83820 that it has been
granted ownership of the bus by the central arbiter. This input is used when the
DP83820 is acting as a bus master.
Initialization Device Select: This pin is sampled by the DP83820 to identify
when configuration read and write accesses are intended for it.
Interrupt A: This signal is asserted low when an interrupt condition as defined
in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable registers
occurs.
Initiator Ready: As a bus master, this signal will be asserted low when the
DP83820 is ready to complete the current data phase transaction. This signal is
used in conjunction with the TRYDN signal. Data transaction takes place at the
rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a
target, this signal indicates that the master has put the data on the bus.
Parity: This signal indicates even parity across AD31-0 and CBEN3-0 including
the PAR pin. As a master, PAR is asserted during address and write data
phases. As a target, PAR is asserted during read data phases.
Parity Error: The DP83820 as a master or target will assert this signal low to
indicate a parity error on any incoming data (except for special cycles). As a bus
master, it will monitor this signal on all write operations (except for special
cycles).
Request: The DP83820 will assert this signal low to request the ownership of
the bus to the central arbiter.
Reset: When this signal is asserted all outputs of DP83820 will be tri-stated
and the device will be put into a known state.
3
Description
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