dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 39

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

4.0 Register Set
4.2 Operational Registers
The DP83820 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to
reserved register locations are ignored. Reads to reserved register locations return undefined values. When mapped to
I/O space, a 256 byte window allows access to all the Operational Registers (00-FCh). When mapped into PCI memory
space, a 4096 byte window is enabled. In addition to access to Operational Registers, the PCI Configuration Registers
can be read at addresses 200-2FCh. Other addresses provide aliased access to Operational Registers or read-only PCI
Configuration Registers.
8C-9Ch
60-88h
offset
ACh
BCh
0Ch
1Ch
2Ch
3Ch
4Ch
5Ch
C0h
C4h
A0h
A4h
A8h
B0h
B4h
B8h
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
50h
54h
58h
C8
RXDP_HI
TXDP_HI
PTSCR
TXCFG
RXCFG
RXDP1
RXDP2
RXDP3
GPIOR
TXDP1
TXDP2
TXDP3
WCSR
MEAR
RXDP
PQCR
RFCR
RFDR
BRAR
BRDR
VRCR
TXDP
VTCR
MIBC
CFG
PCR
VDR
SRR
IMR
MIB
ISR
IER
IHR
tag
CR
(Continued)
Command Register
Configuration Register
EEPROM Access Register
PCI Test Control Register
Interrupt Status Register
Interrupt Mask Register
Interrupt Enable Register
Interrupt Holdoff Register
Transmit Descriptor Pointer Register
Transmit Descriptor Pointer High Dword Register
Transmit Configuration Register
General Purpose I/O Control Register
Receive Descriptor Pointer Register
Receive Descriptor Pointer High Dword Register
Receive Configuration Register
Priority Queueing Control Register
Wake on LAN Control/Status Register
Pause Control/Status Register
Receive Filter/Match Control Register
Receive Filter/Match Data Register
Boot ROM Address
Boot ROM Data
Silicon Revision Register
Management Information Base Control Register
Management Information Base Data Registers
Reserved
Transmit Descriptor Pointer Priority 1 Register
Transmit Descriptor Pointer Priority 2 Register
Transmit Descriptor Pointer Priority 3 Register
Reserved
Receive Descriptor Pointer Priority 1 Register
Receive Descriptor Pointer Priority 2 Register
Receive Descriptor Pointer Priority 3 Register
VLAN/IP Receive Control Register
VLAN/IP Transmit Control Register
VLAN Data register
Reserved
Table 4-2 Operational Register Map
39
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO