dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 24

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

3.0 Functional Description
3.13.3 Transmit Architecture
The Transmit architecture can support a single transmit
queue, or can support multiple transmit queues for
Without Priority Queueing, the device will draw packets
from a single Descriptor list. Only one descriptor pointer is
required. When the CR:TXEN bit is set to 1 (regardless of
the current state), and the DP83820 transmitter is idle, then
With Priority Queueing, the device will draw packets from
up to 4 Descriptor lists. The device has four descriptor
pointers and associated control logic to keep track of when
descriptors are available with valid packet information. In
this case, pulsing CR:TXEN with CR:TXPRI[p] set will
indicate to the DP83820 that a descriptor is available for
Q0
Q1
Q2
Q3
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Figure 3-14 Transmit Architecture without Priority Queueing
Figure 3-15 Transmit Architecture with Priority Queueing
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Transmit Descriptor
Transmit Descriptor
(Continued)
Software/Memory
Software/Memory
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handling priority traffic. The following figures illustrate the
transmit architecture of the DP83820 10/100 Ethernet
Controller with and without Priority Queueing.
DP83820 will read the contents of the current transmit
descriptor
TxDescCache can hold a single fragment pointer/count
combination.
descriptor queue of priority ‘p’. Based on the priority
algorithm in use, the device will draw from the current
highest priority descriptor that has packets available for
transmission. There is no reordering of packets once they
are queued within the internal FIFO.
Hardware
Hardware
Tx DMA
Tx DMA
Current Tx Desc Ptr
into
TxHead
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TxHead
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the
TxDescCache.
Tx Desc Cache
Tx Desc Cache
Current Tx Desc Ptr
Tx Data FIFO
Tx Data FIFO
TXDP1
TXDP2
TXDP3
TXDP4
The
DP83820’s
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