dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 59

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

4.0 Register Set
4.2.22 Receive Filter Logic
The Receive Filter Logic supports a variety of techniques
for qualifying incoming packets. The most basic filtering
options include Accept All Broadcast, Accept All Multicast
and Accept All Unicast packets. These options are enabled
by setting the corresponding bit in the Receive Filter
Control Register, RFCR. Accept on Perfect Match, Accept
on Pattern Match, Accept on Multicast Hash and Accept on
Unicast Hash are more robust in their filtering capabilities,
but require additional programming of the Receive Filter
registers and the internal filter RAM.
4.2.22.1 Accept on Perfect Match
When enabled, the Perfect Match Register is used to
compare against the DA for packet acceptance. The
Perfect Match Register is a 6-byte register accessed
indirectly through the RFCR. The address of the internal
receive filter register to be accessed is programmed
through bits 9:0 of the RFCR. The Receive Filter Data
Register, RFDR, is used for reading/writing the actual data.
RX Filter Address: 000h - Perfect match octets 1-0
Octet 0 of the Perfect Match Register corresponds to the
first octet of the packet as it appears on the wire. Octet 5
corresponds to the last octet of the DA as it appears on the
wire.
The following steps are required to program the RFCR to
accept packets on a perfect match of the DA.
Example: Destination Address of 08-00-17-07-28-55
iow l $RFCR (0000)perfect match register, octets 1-0
iow l $RFDR (0008)write address, octets 1-0
iow l $RFCR (0002)perfect match register, octets 3-2
iow l $RFDR (0717)write address, octets 3-2
iow l $RFCR (0004)perfect match register, octets 5-4
iow l $RFDR (5528)write address, octets 5-4
iow l $RFDR (0606)
($RFEN|$APM) -enable filtering, perfect match
002h - Perfect Match octets 3-2
004h - Perfect Match octets 5-4
(Continued)
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4.2.22.2 Accept on Pattern Match
The Receive Filter Logic provides access to 4 separate
internal RAM-based pattern buffers to be used as
additional perfect match address registers. All pattern
buffers are 128 bytes deep, allowing perfect match on the
first 128 bytes of a packet.
When one or more of the Pattern Match enable bits are set
in the RFCR, a packet will be accepted if it matches the
associated pattern buffer. As indicated above, the pattern
buffers are 128 bytes deep organized as 64 words, where a
word is 18 bits. Bits 17 and 18 of a respective word are
mask bits for byte 0 and byte 1 of the 16-bit data word (bits
15:0). An incoming packet is compared to each enabled
pattern buffer on a byte by byte basis for a specified count.
Masking a pattern byte results in a byte match regardless
of its value (a don’t care). A count value must be
programmed for each pattern buffer to be used for
comparison. The minimum valid count is 1 byte and the
maximum valid count is 128 for all pattern buffers. The
pattern count registers are internal receive filter registers
accessed through the RFCR and the RFDR The Receive
Filter memory is also accessed through the RFCR and the
RFDR. A memory map of the internal pattern RAM is
shown in Figure 4-1.
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