dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 36

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

4.0 Register Set
4.1.8 Configuration Subsystem Identification Register
The CFGSID allows system software to distinguish between different subsystems based on the same PCI silicon. The
values in this register can be loaded from the EEPROM if configuration is enabled.
4.1.9 Boot ROM Configuration Register
4.1.10 Capabilities Pointer Register
This register stores the capabilities linked list offset into the PCI configuration space.
31-16
31-16
15-11
15-0
10-1
31-8
7-0
bit
bit
bit
0
ROMBASE
ROMSIZE
SDEVID
SVENID
ROMEN
CLOFS
tag
tag
tag
Offset: 2Ch
Offset: 30h
Offset: 34h
(Continued)
Tag: CFGSID
Tag: CFGROM
Tag: CAPPTR
Subsystem Device ID
Subsystem Vendor ID
ROM Base Address
ROM Size
Unused
ROM Enable
Capabilities List Offset
description
description
description
Access: Read Only
Access: Read Write
Access: Read Only
Loaded from the EEPROM
Loaded from the EEPROM
Set to the base address for the boot ROM.
Read only. Set to 0 indicating a requirement for 64K bytes of Boot ROM
space
unused (reads return 0)
This is used by the PCI BIOS to enable accesses to boot ROM. This allows
the DP83820 to share the address decode logic between the boot ROM
and itself. The BIOS will copy the contents of the boot ROM to system RAM
before executing it. Set to 1 enables the address decode for boot ROM
disabling access to operational target registers.
unused (reads return 0)
Offset into PCI configuration space for the location of the first item in the
Capabilities Linked List, set to 40h to point to the PMCAP register.
Size: 32 bits
Size: 32 bits
Size: 32 bits
36
usage
usage
usage
Hard Reset: ?
Hard Reset: 00000000h
Hard Reset: 00000040h
Soft Reset: unchanged
Soft Reset: unchanged
Soft Reset: unchanged
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