tspc603r ATMEL Corporation, tspc603r Datasheet - Page 40

• Manufacturer Part Number: tspc603r
• Description: Powerpc 603e Risc Microprocessor Family Pid7t-603e
• Manufacturer: ATMEL Corporation

Table 12-2.
40
Exception Type
Program
Floating-point
unavailable
Decrementer
Reserved
System call
Trace
Reserved
Reserved
Instruction
translation miss
Data load
translation miss
Data store
translation miss
TSPC603R
Exceptions and Conditions (Continued)
00A00–00BFF
00E10–00FFF
Vector Offset
00C00
00D00
00E00
00700
00800
00900
01000
01100
01200
(hex)
Causing Conditions
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
A floating-point unavailable exception is caused by an attempt to execute a floating-point
instruction (including floating-point load, store, and more instructions) when the floating-
point available bit is disabled, (MSR[FP] = 0)
The decrementer exception occurs when the most significant bit of the decrementer (DEC)
register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit
–
A system call exception occurs when a System Call (sc) instruction is executed
A trace execution is taken when MSR[SE] = 1 or when the currently completing instruction
is a branch and MSR[BE] = 1
The 603e does not generate an exception to this vector. Other PowerPC processors may
use this vector for floating-point assist exceptions
–
An instruction translation miss exception is caused when an effective address for an
instruction fetch cannot be translated by the ITLB
A data load translation miss exception is caused when an effective address for a data load
operation cannot be translated by the DTLB
A data store translation miss exception is caused when an effective address for a data store
operation cannot be translated by the DTLB; or where a DTLB hit occurs, and the change
bit in the PTE must be set due to a data store operation
• Floating-point enabled exception – A floating-point enabled exception condition
• Illegal instruction – an illegal instruction program exception is generated when
• Privileged instruction – a privileged instruction type program exception is
• Trap – a trap type program exception is generated when any of the conditions
is generated when the following condition is met: (MSR[FE0] | MSR[FE1]) &
FPSCR[FEX] is 1 FPSER[FEX] is set by the execution of a floating-point
instruction that causes an enabled exception or by the execution of one of the
“move to FPSCR” instructions that results in both an exception condition bit
and its corresponding enable bit being set in the FPSCR
execution of an instruction is attempted with an illegal opcode or illegal
combination of opcode and extended opcode fields (including PowerPC
instructions not implemented in the 603e), or when execution of an optional
instruction not provided in the 603e is attempted (these do not include those
optional instructions that are treated as no-ops)
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR], is set. In the 603e, this exception is
generated for mtspr or mfspr with an invalid SPR field if SPR[0] = 1 and
MSR[PR] = 1. This may not be true for all PowerPC processors
specified in a trap instruction is met
5410B–HIREL–09/05