tspc603r ATMEL Corporation, tspc603r Datasheet - Page 34

• Manufacturer Part Number: tspc603r
• Description: Powerpc 603e Risc Microprocessor Family Pid7t-603e
• Manufacturer: ATMEL Corporation

34
TSPC603R
Note that this grouping of the instructions does not indicate which execution unit executes a par-
ticular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions
operate on single-precision (one word) and double-precision (one double word) floating-point
operands. The PowerPC architecture uses instructions that are four bytes long and
word-aligned. It provides for byte, half-word, and word operand loads and stores between the
memory and a set of 32 GPRs. It also provides for word and double-word operand loads and
stores between the memory and a set of 32 Floating-point Registers (FPRs).
Computational instructions do not modify the memory. To use a memory operand in a computa-
tion and then modify the same or another memory location, the memory contents must be
loaded into a register, modified, and then written back to the target location with distinct
instructions.
PowerPC processors follow the program flow when they are in the normal execution state. How-
ever, the flow of instructions can be interrupted directly by the execution of an instruction or by
an asynchronous event. Either kind of exception may cause one of several components of the
system software to be invoked.
These simple addressing modes allow efficient address generation for memory accesses. Cal-
culation of the effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the memory operand is considered to wrap around
from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry over from bit 0 is ignored in 32-bit implementations.
• Memory Control Instructions
• Calculating Effective Address
segment registers
The Effective Address (EA) is the 32-bit address computed by the processor when executing
a memory access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
– Supervisor-level cache management instructions
– User-level cache instructions
– Segment register manipulation instructions
– Translation lookaside buffer management instructions
– EA = (RA|0) + offset (including offset = 0) (register indirect with immediate index)
– EA = (RA|0) + rB (register indirect with index)
–
these instructions provide control of caches, TLBs, and
5410B–HIREL–09/05