tspc603r ATMEL Corporation, tspc603r Datasheet - Page 23

• Manufacturer Part Number: tspc603r
• Description: Powerpc 603e Risc Microprocessor Family Pid7t-603e
• Manufacturer: ATMEL Corporation

11.3
11.3.1
Table 11-2.
Notes:
Figure 11-1. SYSCLK Input Timing Diagram
5410B–HIREL–09/05
1
2,3
4
Number
Figure
3. Leakage currents are measured for nominal OV
Dynamic Characteristics
1. Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V.
2. Cycle-to-cycle jitter is guaranteed by design.
3. Timing is guaranteed by design and characterization and is not tested.
4. The PLL relock time is the maximum amount of time required for PLL lock after a stable V
5. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen so that the resulting SYSCLK (bus) fre-
SYSCLK
Clock AC Specifications
and OV
reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subse-
quently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after
the PLL relock time (100 µs) during the power-on reset sequence.
quency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0-3] signal description for valid PLL_CFG[0-3] settings.
Characteristics
Processor Frequency
VCO Frequency
SYSCLK (bus)
Frequency
SYSCLK Cycle Time
SYSCLK Rise and
Fall Time
SYSCLK Duty Cycle
(1.4V measured)
SYSCLK Jitter
603R Internal PLL
Relock Time
Clock AC Timing Specifications
-55°C ≤ T
DD
vary by either +5% or -5%)
C
≤ 125°C
Table 11-2
VM
Min
150
300
25
15
40
CBGA 255, HiTCE CBGA
–
–
–
166 MHz
provides the clock AC timing specifications as defined in
255, CI-CGA 255 and
1
±
Max
66.7
166
332
100
CERQUAD
30
60
150
2
VM
(1)(2)(3)(4)
VM = Midpoint Voltage (1.4V)
33.3
13.3
Min
150
300
40
–
–
–
200 MHz
DD
with
and V
±
Max
66.7
200
400
100
30
60
150
VM
2
V
DD
DD
= A
or both OV
CVil
33.3
13.3
Min
180
360
40
V
–
–
–
233 MHz
DD
= 2.5V ±5%; O
CBGA 255, HiTCE CBGA 255 and CI-CGA 255
±
Max
233
466
100
75
30
60
150
2
DD
CVih
and V
33.3
13.3
Min
180
360
40
–
–
–
266 MHz
DD
. Same variation (for example, both V
V
DD
±
Max
266
532
100
75
30
60
150
2
= 3.3 ±5%V, GND = 0V,
DD
2
, OV
Figure
33.3
13.3
Min
180
360
40
–
–
–
300 MHz
DD
, AV
11-1.
TSPC603R
±
Max
300
600
100
75
30
60
150
DD
2
and SYSCLK are
3
MHz
MHz
Unit
MHz
ns
ns
ps
µs
%
Note
(3)(4)
DD
(5)
(5)
(5)
(1)
(3)
(2)
23