tspc603r ATMEL Corporation, tspc603r Datasheet
tspc603r
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tspc603r Summary of contents
Page 1
... The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The interface protocol allows multiple masters to compete for system resources through a central external arbiter. The device supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/Os. ® PowerPC 603e RISC Microprocessor Family PID7t-603e TSPC603R Rev. 5410B–HIREL–09/05 ...
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... Cerquad: – Full military temperature range (T – Industrial temperature range – Commercial temperature ranges ( • Internal I/O Power Supply = 2.5 ±5% // 3.3V ±5% A suffix CERQUAD 240 Ceramic Leaded Chip Carrier Cavity up CERQUAD 240 TSPC603R 2 = -55° +125° -40° +110° -55° ...
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... Unit Completion Unit Dispatch Unit Load/ Integer Gen Gen Store Unit Reg Re- Unit Unit name D MMU 16K Data Cache Bus Interface Unit 32b Address System Bus TSPC603R Branch Unit FP FP Float Re- Reg Unit name File I MMU 16K Inst. Cache 64b Data 3 ...
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... Signal Description Figure 5-1 on page TSPC603R and indicate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO, comply with the subset P-1149.1 of the IEEE testability bus standard. The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use ...
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... TERMINATION CLOCKS POWER SUPPLY INDICATOR 6. Detailed Specifications This specification describes the specific requirements for the microprocessor TSPC603R, in compliance with MIL-STD-883 class B or Atmel standard screening. 7. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein. ...
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... Parameter Core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature Junction operating temperature specific to Cerquad TSPC603R 6 18, ”Recommended Operating Conditions” on page and Figure 5-1 on page 47.) Absolute Maximum Ratings for the 603R 1. Caution: The input voltage must not be greater than OV including during power-on reset ...
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... P is the power dissipated by the device ”Recommended Operating Conditions” on page of 85°C and a consumption (P) of 3.6 Watts, the junction temperature of the a 85°C + (0.095°C/Watt + 1°C/Watt + Figure 8-1. TSPC603R should be maintained at a lower value than j 6. ...
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... This configuration enables dissipation through the PCB. The thermal characteristics for a wire-bond CERQUAD package are as follows: • Thermal resistance (junction to bottom of the case) (typical • Thermal resistance (junction to top of the case) is typically 16°C/W TSPC603R 8 CBGA Thermal Management Example 7 6 ...
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... 110°C + (2 × 2.5 = 125°C j TSPC603R and R are user values, and can vary con 3°C/W and Ta is 110° can be ...
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... Full Power Mode with DPM Enabled Full power mode with DPM enabled (HID0[11] = 1); provides on-chip power management with- out affecting the functionality or performance of the 603R • Required functional units are operating at full processor speed TSPC603R 10 summarizes the four power states. Activation Method – ...
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... There are several methods for returning to full-power mode: – Assert INT, SPI, MCP or decrementer interrupts – Assert hard reset or soft reset • Transition to full-power takes no more than a few processor cycles • The PLL is running and locked to SYSCLK 5410B–HIREL–09/05 TSPC603R 11 ...
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... HID0 mode bit. Later on, the power management mode is invoked by setting the MSR[POW] bit. To provide a clean transition into and out of the power management mode, the stmsr[POW] should be preceded by a sync instruction and fol- lowed by an isync instruction. TSPC603R 12 5410B–HIREL–09/05 ...
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... AV = 2.5V 2.625V using a worst-case instruction mix. DD (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA TSPC603R = 3.3 ±5%V, GND = 0V, 0°C ≤ 200 MHz 233 MHz 266 MHz 2.5 3 3.5 4 4.6 5.3 1.7 1.8 2 120 140 ...
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... Figure 10-1. CBGA 255, HiTCE CBGA 255 and CI–CGA 255 Top View Substrate Assembly TSPC603R 14 Pin matrix top view View Die Not to scale CBGA 255, CBGA HiTCE 255 ...
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... F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 inputs supply power to the processor core. DD TSPC603R Active I/O High I/O Low Input ...
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... F03 Notes: 1. These are test signals for factory use only and must be pulled (not connected) in the 603e BGA package; internally tied to GND in the 603R BGA package to indicate to the power sup- ply that a low-voltage processor is present. TSPC603R 16 Active Low Low ...
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... GND 49 DP7 50 DL23 51 DL24 52 OGND 53 OVDD 54 55 DL25 DL26 56 DL27 57 DL28 58 VDD 59 OGND 60 5410B–HIREL–09/05 TOP VIEW TSPC603R 180 TT4 179 A0 178 A2 177 VDD 176 A4 175 A6 174 A8 173 OVDD 172 GND 171 OGND 170 A10 169 A12 168 A14 167 ...
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... DPE 217 DRTRY 156 GBL 1 HRESET 214 TSPC603R 18 CERQUAD Pin Number GND 9, 19,29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 ...
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... These are test signals for factory use only and must be pulled inputs supply power to the I/O drivers and V DD family may use different OV 5410B–HIREL–09/05 inputs supply power to the processor core. Future members of the 603 DD and V input levels TSPC603R for normal machine operation ...
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... Data Bus Parity DP[0-7] Data Parity Error DPE Data Retry DRTRY TSPC603R 20 Signal Function If output, physical address of data to be transferred If input, represents the physical address of a snoop operation Represents the state of data, during a data write operation if output, or during a data read operation if input ...
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... Instruction execution should stop after execution of a tlbsync instruction Selects the principal operations of the test-support circuitry Provides an asynchronous reset of the TAP controller For memory accesses, these signals along with TBST indicate the data transfer size for the current bus operation TSPC603R Signal Type I/O Input ...
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... TS, ABB, DBB, and ARTRY) IN Notes: 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals). 2. Capacitance is periodically sampled rather than 100% tested. TSPC603R 22 Signal Function If output, begun a memory bus transaction and the address bus and transfer attribute signals are valid If input, another master has begun a bus transaction and the address bus and ...
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... VM VM CVil VM = Midpoint Voltage (1.4V) TSPC603R and V . Same variation (for example, both Figure 11-1. = 2.5V ±5 3.3 ±5%V, GND = 0V CBGA 255, HiTCE CBGA 255 and CI-CGA 255 266 MHz 300 MHz Max Min ...
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... This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100 µs) during the power-on reset sequence. Figure 11-2. Input Timing Diagram SYSCLK All inputs TSPC603R 24 provides the input AC timing specifications for the 603R as defined in 11-3. (1) ...
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... SYSCLK + 1 – 1 – 2 TSPC603R VM 11c Figure = 3.3 ±5%V, GND = 0V CBGA 255, HiTCE CBGA 255 and CI-CGA 255 233, 266 MHz 300 MHz Min Max Min Max 1 – 1 – – 9 – ...
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... The output signal transitions from GND The nominal precharge width for ABB and DBB is 0.5 × The nominal precharge width for ARTRY is 1 × t Figure 11-4. Output Timing Diagram SYSCLK 12 ALL OUTPUTS (Except TS, ABB, DBB, ARTRY) TS ABB, DBB ARTRY TSPC603R pF pF 0.8V sysclk . sysclk ...
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... TCK Midpoint Voltage (1.4V) TCK TRST = A = 2.5V ±5 Max Unit 16 MHz – ns – – ns – ns – ns – – ns – TSPC603R = 3.3 ±5%V, DD Notes (1) (2) (2) (3) ( ...
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... The programming models incorporate 32 GPRs, 32 FPRs, Special-purpose Registers (SPRs) and several miscellaneous registers. Each PowerPC microprocessor also has its own unique set of Hardware Implementation (HID) registers. TSPC603R 28 VM TCK Data Inputs ...
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... Registers (SRs). To speed access, the 603R implements the segment registers as two arrays; a main array (for data memory accesses) and a shadow array (for instruction memory accesses). Loading a segment entry with the Move to Segment Register (STSR) instruction loads both arrays. 5410B–HIREL–09/05 TSPC603R 29 ...
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... The machine status Save/Restore Register 1 (SRR1 32-bit register used to – The 32-bit SPRG0-SPRG3 registers are provided for operating system use. – The External Access Register (EAR 32-bit register that controls access to the TSPC603R 30 Figure 12-1 on page address and to hold the return address after branch and link instructions. The bits wide in 32-bit implementations ...
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... PLL configuration signals. address that is compared to instruction addresses in the dispatch queue. When an address match occurs, an instruction address breakpoint exception is generated. shows all the 603R registers available at the user and supervisor level. The number TSPC603R 31 ...
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... XER SPR1 Link Register LR SPR8 Count Register CTR SPR9 Time Base Facility (for reading) TBL TBR 268 TBU TBR 269 TSPC603R 32 SUPERVISOR MODEL Configuration Registers Hardware Machine State Implementation Registers (1) Register MSR SPR1 008 HID0 HID1 SPR1 009 Memory Management Registers ...
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... TSPC603R 33 ...
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... Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry over from bit 0 is ignored in 32-bit implementations. TSPC603R 34 these instructions provide control of caches, TLBs, and – ...
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... Each line contains eight 32-bit words. Note that the PowerPC architecture defines the term block as the cacheable unit. For the 603R, the block size is equivalent to a cache line. A block diagram of the data cache organization is shown in 5410B–HIREL–09/05 TSPC603R Figure 12-2 on page 36. 35 ...
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... The snoop access is granted first access to the tags. The load or store then occurs on the clock following snoop. Figure 12-2. Data Cache Organization 128 sets Block 0 Address Tag 0 Block 1 Address Tag 1 Block 2 Address Tag 2 Block 3 Address Tag 3 TSPC603R 36 State Words 0-07 State Words 0-07 State Words 0-07 State Words 0-07 8 words/block Figure 12-2 on ...
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... Once the exception is processed, execution resumes at the address of the faulting instruction ( alternate address provided by the exception handler). When an exception is taken due to a trap or system call instruction, execution resumes at an address provided by the handler. 5410B–HIREL–09/05 TSPC603R 37 ...
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... Table 12-2. Exceptions and Conditions Vector Offset Exception Type (hex) Reserved 00000 System reset 00100 Machine check 00200 TSPC603R 38 Table 12-1. PowerPC 603R Microprocessor Exception Classifications Precise/Imprecise Imprecise Precise Precise Table 12-1 Table 12-1 includes no synchronous imprecise instructions. Causing Conditions – ...
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... The operand of a single-register load or store operation is not aligned, and the 603e is in little-endian mode • The instruction is lmw, stmw, lswi, lwsx, stswi, stswx and the 603e is in little- endian mode • The operand of dcbz is in storage that is write-through-required, or caching inhibited TSPC603R 39 ...
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... Data load 01100 translation miss Data store 01200 translation miss TSPC603R 40 Causing Conditions A program exception is caused by one of the following exception conditions, which correspond to bit settings in SRR1 and arise during execution of an instruction: • Floating-point enabled exception – A floating-point enabled exception condition is generated when the following condition is met: (MSR[FE0] | MSR[FE1]) & ...
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... An instruction address breakpoint exception occurs when the address (bits 0-29) in the IABR matches the next instruction to complete in the completion unit, and the IABR enable bit (bit 30) is set system management interrupt is caused when MSR[EE and the SMI input signal is asserted – TSPC603R 41 ...
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... Execution of most load/store instructions is also pipelined. The load/store unit has two pipeline stages. The first stage is for effective address calculation and MMU translation and the second stage is for accessing the data in the cache. TSPC603R 42 5410B–HIREL–09/05 ...
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... VCO. The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1 bus mode). 5410B–HIREL–09/05 TSPC603R 43 ...
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... Bus-to-Core Core-to VCO PLL_CFG[0-3] Multiplier 0100 2x 0101 2x 0110 2.5x 1000 3x 1110 3.5x TSPC603R 44 13-1, the horizontal scale represents the bus frequency (SYSCLK) and the vertical Bus Bus Bus 25 MHz 33.33 MHz 40 MHz - - - - - - - - - - 160 - - (320) 150 180 - (300) ...
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... Figure 14-1. The circuit should pin to ensure it filters out as much noise as possible. pin, followed by the 10 µF capacitor, and µF 0.1 µF GND TSPC603R Bus 66.67 MHz – – – – – – – – – – input V ...
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... The snooped address and transfer attribute inputs are: A[0-3], AP[0-3], TT[0-4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. TSPC603R 46 and O pin of the 603e also recommended that ...
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... CBGA, HiTCE CBGA and the Cerquad packages. 15.1 HiTCE CBGA Package Parameters The package parameters are as provided in the following list. The package type is 21 mm, 255- lead HiTCE Ceramic Ball Array (HiTCE CBGA). Package outline Interconnects Pitch Maximum module height 5410B–HIREL–09/ × 255 1.27 mm 3.08 mm TSPC603R 47 ...
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... Figure 15-1. Mechanical Dimensions of the HiTCE CBGA Package Ball A1 Index 0 TSPC603R 48 provides the mechanical dimensions and bottom surface nomenclature of the 255X 0 0. ...
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... 0.300 0.150 S TSPC603R - T - Notes: 1. Dimensioning and tolerancing per ASME Y14.5M - 1994 2. controlling dimension: millimeter MILLIMETERS DIM MIN MAX MIN A 21.000 BSC B 21.000 BSC C 2.450 3.000 0.097 D 0.820 0.930 0.032 G 1.270 BSC H 0 ...
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... The package parameters are as provided in the following list. The package type is 21 mm, 255-lead ceramic ball grid array (CI-CGA). Package outline Interconnects Pitch Typical module height 15.3.1 Mechanical Dimensions of the CI-CGA Package Figure 15-3 CGA package. TSPC603R 50 provides the mechanical dimensions and bottom surface nomenclature of the CI × 255 1.27 mm 3.84 mm 5410B–HIREL–09/05 ...
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... TSPC603R Notes: 1. Dimensioning and tolerancing per ASME Y14.5M—1994 2. Controlling dimension: millimeter Millimeters -T- Dim Min A 21.000 BSC B 21.000 BSC C 3.84 BSC D 0.790 G 1.270 BSC H 1.545 K 0.635 BSC N 5.000 P 7.000 R 3 ...
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... CERQUAD 240 Package Figure 15-4. Mechanical Dimensions of the Wire-bond CERQUAD Package Die TOP U 180 181 240 tips 0. TSPC603R 52 Wire Bonds Ceramic Body Alloy 42 Leads S VIEW AC 121 4 Places 120 0. Datum H Plane 0.10 View AE Seating T Plane AB Datum Θ ...
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... Screening level Standard B/Q: MIL-PRF-38535, class Q U: Upscreening PC603R Screening level Standard B/Q : MIL-PRF-38535, class Q TSPC603R L (C) Revision level Bus divider (to be confirmed) L: any bus at 75 MHz Maximum internal processor speed 6 : 166 MHz 8 : 200 MHz 10: 233 MHz 12: 266 MHz 14: 300 MHz (C ) ...
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... Revision Number Date Substantive Change(s) B 07/2005 Added HiTCE package for PowerPC 603R This document is a merge of TSPC603R in CBGA255/CI-CGA 255 package (ref 2125B) and A 10/2004 TSPC603R in Cerquad package (ref 2127A) TSPC603R 54 This datasheet contains target and goal specifications for discussion with the customer and application validation ...
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... CBGA 255 and CI-CGA 255 Packages ....................................................................7 8.2 HiTCE CBGA Package .............................................................................................8 8.3 CERQUAD 240 Package .........................................................................................8 9.1 Dynamic Power Management ..................................................................................9 9.2 Programmable Power Modes .................................................................................10 9.3 Power Management Modes ...................................................................................10 9.4 Power Management Software Considerations .......................................................12 9.5 Power Dissipation ...................................................................................................13 9.6 Marking ...................................................................................................................13 10.1 CBGA 255 and CI-CGA 255 Packages ................................................................13 10.2 CERQUAD 240 Package .....................................................................................17 11.1 General Requirements .........................................................................................22 11.2 Static Characteristics ............................................................................................22 11.3 Dynamic Characteristics .......................................................................................23 TSPC603R i ...
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... Functional Description .......................................................................... 28 13 Preparation for Delivery ........................................................................ 43 14 System Design Information .................................................................. 45 15 Package Mechanical Data ..................................................................... 47 16 Ordering Information ............................................................................. 53 17 Definitions .............................................................................................. 54 18 Document Revision History .................................................................. 54 TSPC603R ii 11.4 JTAG AC Timing Specifications ...........................................................................27 12.1 PowerPC Registers and Programming Model ......................................................28 12.2 Instruction Set and Addressing Modes .................................................................33 12.3 Cache Implementation .........................................................................................35 12.4 Memory Management ..........................................................................................41 13 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life © Atmel Corporation 2005. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. PowerPC names may be trademarks of others. Atmel Operations ...
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... TSPC603R iv 5410B–HIREL–09/05 ...