tspc603r ATMEL Corporation, tspc603r Datasheet - Page 27

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tspc603r

Manufacturer Part Number
tspc603r
Description
Powerpc 603e Risc Microprocessor Family Pid7t-603e
Manufacturer
ATMEL Corporation
Datasheet

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11.4
Table 11-5.
Notes:
5410B–HIREL–09/05
Number
10
11
12
13
1
2
3
4
5
6
7
8
9
JTAG AC Timing Specifications
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
Characteristics
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4V
TCK rise and fall times
TRST setup time to TCK rising edge
TRST assert time
Boundary scan input data setup time
Boundary scan input data hold time
TCK to output data valid
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
TCK to TDO high impedance
JTAG AC Timing Specifications (independent of SYSCLK);
GND = 0V, C
Figure 11-5. Clock Input Timing Diagram
Figure 11-6. TRST Timing Diagram
L
= 50 pF, -55°C ≤ T
TCK
TCK
TRST
3
C
≤ 125°C
VM = Midpoint Voltage (1.4V)
3
62.5
Min
25
13
40
27
25
0
4
3
0
4
3
0
6
5
VM
V
DD
= A
2
4
V
Max
DD
16
25
24
24
15
3
= 2.5V ±5%; O
1
VM
VM
2
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
DD
TSPC603R
= 3.3 ±5%V,
VM
Notes
(1)
(2)
(2)
(3)
(3)
27

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