gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 93

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.9 Reset Circuit
6.2.9.1 Power On/Fail Reset
6.2.9.2 External Reset
MiDAS1.1 Family
general, most register bits go to their reset values irrespective of the current states, but there are a few
flags whose state depends on the source of reset. The user can use these flags to determine the cause
of reset using software. There are three ways of putting the device into reset state. They are Power
on/fail reset, External reset, and Watchdog reset as shown in
out of tolerance. While powering up, internal circuits will hold the device in a reset state until V
above the V
internal reset circuit will then count 65,536 clocks to allow time for power and the oscillator to stabilize.
The CPU will then exit the reset state. No external components are needed to generate a power on
reset. During power-down or during a severe power glitch, as V
generate its own reset. It will hold the reset state as long as power remains below the threshold. This
reset will occur automatically, needing no action from the user or from the software.
RESET pin must be held for at least 6 machine cycles (24 clocks) to ensure detection of a valid RESET
low. The reset circuitry then synchronously applies the internal reset signal. Thus the reset is a
Figure 6-20 Three Reset Resources
The user has several hardware related options for placing the MiDAS1.1 family into reset state. In
The MiDAS1.1 family incorporates a precision band-gap voltage reference to determine when V
The device continuously samples the RESETB pin at state S4 of every machine cycle. Therefore the
RESETB
Clock
V
DD
RST
reset threshold (2.0V). Once V
16 bits Counter
LVD
Initialize
WDT
(Min. 24 C locks Period)
External RESET
Generation
POR
256 Clocks
Delay
LVD RESET
Generation
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DD
is above this level, the oscillator will begin running. An
WDT RESET
Generation
Figure
WTRF
EWT
DD
falls below V
6-20.
RST
, the CPU will also
Internal RESET
DD
rises
DD
is