gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 55

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.4 Timer 0/1
6.2.4.1 Timer/Counter 0
6.2.4.1.1 Time-base
6.2.4.1.2 Mode 0
MiDAS1.1 Family
upper 8-bit register TH0 and the lower 8-bit register TL0.
be thought of as 1/12 of the system clock. In the “Counter” mode, the register is incremented on the
falling edge of the external input pin, T0 in case of Timer 0. The T0 input is sampled at S3 state of 12-
clock system. If the sampled value is high in one machine cycle and low in the next, then a valid high-
to-low transition on the pin is recognized and the count register is incremented. Since it takes 24 clocks
(12-clock system) to recognize a negative transition on the pin, the maximum rate at which counting will
take place is 1/24 of the master clock frequency. In either the “Timer” or “Counter” mode, the count
register will be updated at S2 state. Therefore, in the “Timer” mode, the recognized negative transition
on pin T0 can cause the count register value to be updated only in the machine cycle following the one
in which the negative edge was detected.
has one selection bit for its own; bit 2 of TMOD selects the function for Timer/Counter 0. In addition the
Timer/Counter 0 can be set to operate in any one of four possible modes. The mode selection is done
by bits M0 and M1 in the TMOD SFR.
operate like the standard 80C52 family, counting at the rate of 1/12 of the clock speed (F
will ensure that timing loops on the MiDAS1.1 family and the standard 80C52 family can be matched.
This is the default mode of operation of the MiDAS1.1 timers.
mode, we have a 13-bit timer/counter. The 13-bit counter consists of 8 bits of TH0 and the lower 5 bits
of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored.
moves from 1 to 0, then the count in the TH0 register is incremented. When the count in TH0 moves
from FFh to 00h, the overflow flag TF0 in TCON SFR is set. The counted input is enabled only if TR0 is
set and either GATE=0 or INT0B=1. When C/T is cleared to 0, then it will count clock cycles, and if C/T
The MiDAS1.1 family has two 16-bit programmable timer/counters.
The Timer/Counter 0 has two 8-bit registers which form the 16-bit counting register. They are the
When configured as a “Timer”, the timer counts clock cycles. The timer clock can be programmed to
The “Timer” or “Counter” function is selected by the “C/T” bit in the TMOD SFR. The Timer/Counter 0
The MiDAS1.1 family gives the user one time base for the timer. The timers can be programmed to
In Mode 0, the timer/counter 0 operates as an 8-bit counter with a divide-by-32 prescaler. In this
The negative edge of the clock increments the counts in the TL0 register. When the fifth bit in TL0
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/12). This