gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 48
gc80c510
Manufacturer Part Number
gc80c510
Description
Eprom/rom 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C510.pdf
(211 pages)
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6.2.2 LVD (Low Voltage Detector)
6.2.2.1 Power–On Reset (POR)
6.2.2.2 Power-Fail Reset
the power–on reset state while V
2.3V), the microcontroller will restart the oscillation of the external crystal and count 65,536 clock cycles.
The processor will then begin software execution at location 0000h.
voltage is in a known good state. The processor will exit the reset condition automatically once the
above conditions are met. This happens automatically, needing no external components or action.
Execution begins at the standard reset vector address of 0000h.
in PCON[4]). Since all resets cause a vector to location 0000h, the POR flag allows software to
acknowledge that power failure was the reason for a reset. Software should clear the POR bit after
reading it. When a reset occurs, software will be able to determine if a power cycle was the cause.
condition will remain while power is below the threshold (V
threshold (V
below V
Figure 6-6 Power-On Reset/Power-fail Reset and Power-fail interrupt (V
Members of the MiDAS1.1 family incorporate an internal voltage reference which holds the CPU in
This helps the system maintain reliable operation by only permitting processor operation when
Software can determine that a Power–On Reset has occurred using the Power–On Reset flag (POR
When power fails (below V
RST
appears the same as a power up.
RST
), a full power–on reset will be performed. Thus a brown-out that causes V
POR Pulse
5.0
2.3
0
RST
DD
), the power monitor will invoke the reset state again. This reset
A
is out of tolerance. Once V
2.3V
Page 48 of 211
RST
DD
). When power returns above the reset
has risen above the threshold (V
2.3V
B
RST
TIME
Functional Description
=2.3V)
DD
to drop
RST
=
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