mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 8

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

MPC8568E Overview
1.2.9
The MPC8568E supports two high-speed I/O interface standards: serial RapidIO and PCI Express. It can
be configured as x1/x4 SRIO and 1x/2x/4x PCI Express simultaneously with the following limitation:
If x8 PCI Express is needed, then SRIO is not available due to the pin multiplex limitation.
1.2.10 Serial RapidIO
The serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.2. RapidIO is
a high-performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can be
used in a variety of applications as an open standard. The RapidIO architecture has a rich variety of
features including high data bandwidth, low-latency capability, and support for high-performance I/O
devices, as well as support for message-passing and software-managed programming models. Key features
of the serial RapidIO interface unit include:
The RapidIO messaging unit supports two inbox/outbox mailboxes (queues) for data and one doorbell
message structure. Both chaining and direct modes are provided for the outbox, and messages can hold up
to 16 packets of 256 bytes, or a total of 4 Kbytes.
1.2.11 PCI Express Interface
The MPC8568E supports a PCI Express interface compatible with the PCI Express Base Specification
Revision 1.0a. It is configurable at boot time to act as either root complex or endpoint.The physical layer
of the PCI Express interface operates at a 2.5-Gbaud data rate per lane.
Other features of the PCI Express interface include:
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Both SRIO and PCI-Express are limited to use the same clock and are limited to 2.5G.
support it).
Support for RapidIO Interconnect Specification, Revision 1.2 (all transaction flows and priorities)
Both 1x and 4x LP-serial link interfaces, with transmission rates of 1.25, 2.5, and 3.125 Gbaud
(data rates of 1.0, 2.0, and 2.5 Gbps) per lane
Auto detection of 1x or 4x mode operation during port initialization
34-bit addressing and up to 256-byte data payload
Receiver-controlled flow control
Support for RapidIO error injection
x8, x4, x2, and x1 link widths supported
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing and 256-byte maximum payload size
Full 64-bit decode with 32-bit wide windows
Spread spectrum clocking can not be used because SRIO doesn't support this (PCI-Express does
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
High Speed I/O Interfaces
Freescale Semiconductor