mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 69

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

Figure 47
It assumes the DC levels of the clock driver are compatible with MPC8568E SerDes reference clock
input’s DC requirement.
13.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
The detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based
on application usage. Refer to the following sections for detailed information:
13.2.4.1
SD_REF_CLK/SD_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
Freescale Semiconductor
•
•
Single-Ended
CLK Driver Chip
Clock Driver
Section 14.2, “AC Requirements for PCI Express SerDes
Section 15.2, “AC Requirements for Serial RapidIO SD_REF_CLK and
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
AC Requirements for SerDes Reference Clocks
Spread Spectrum Clock
CLK_Out
Figure 47. Single-Ended Connection (Reference Only)
33 Ω
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
100 Ω differential PWB trace
SD_REF_CLK
SD_REF_CLK
Clocks”
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
SD_REF_CLK”
MPC8568E
SerDes Refer.
CLK Receiver
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