mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 68

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

High-Speed Serial Interfaces (HSSI)
Figure 46
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
MPC8568 SerDes reference clock input’s DC requirement, AC-coupling has to be used.
assumes that the LVPECL clock driver’s output impedance is 50Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8568 SerDes
reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).
For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock
input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω. Please
consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a
particular clock driver chip.
68
LVPECL CLK
Driver Chip
Clock Driver
Clock Driver
Figure 46. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
CLK_Out
CLK_Out
R1
R1
100 Ω differential PWB trace
R2
R2
10 nF
10 nF
SD_REF_CLK
SD_REF_CLK
50 Ω
50 Ω
Freescale Semiconductor
MPC8568E
SerDes Refer.
CLK Receiver
Figure 46