mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 3

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

These features are described in greater detail in subsequent sections.
1.2
This section contains a high-level view of the MPC8568E architecture.
1.2.1
The MPC8568E contains a high-performance 32-bit Book E–enhanced e500v2 core that implements
Power Architecture. In addition to 36-bit physical addressing, this version of the e500 core includes:
The MPC8568E also contains 512 Kbytes of L2 cache/SRAM, as follows:
Freescale Semiconductor
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QUICC Engine
Integrated security engine with XOR acceleration
Two integrated 10/100/1Gb enhanced three-speed Ethernet controllers (eTSECs) with TCP/IP
acceleration and classification capabilities
DDR/DDR2 memory controller
Table lookup unit (TLU) to access application-defined routing topology and control tables
32-bit PCI controller
A 1x/4x serial RapidIO™ and/or x1/x2/x4 PCI Express interface. If x8 PCI Express is needed, then
RapidIO is not available due to the limitation of the pin multiplexing.
Programmable interrupt controller (PIC)
Four-channel DMA controller, two I
Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for
single-precision (32-bit) floating-point instructions.
Eight-way set-associative cache organization with 32-byte cache lines
Flexible configuration (can be configured as part cache, part SRAM)
External masters can force data to be allocated into the cache through programmed memory ranges
or special transaction types (stashing).
SRAM features include the following:
— I/O devices access SRAM regions by marking transactions as snoopable (global).
— Regions can reside at any aligned location in the memory map.
— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line
MPC8568E Architecture Overview
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
accesses.
e500 Core and Memory Unit
The MPC8568E and MPC8567E are also available without a security
engine, in a configuration known as the MPC8568 and MPC8567. All
specifications other than those relating to security apply to the MPC8568
and MPC8567 exactly as described in this document.
2
C controllers, DUART, and local bus controller (LBC)
NOTE
MPC8568E Overview
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