mpc8568e Freescale Semiconductor, Inc, mpc8568e Datasheet - Page 136

• Manufacturer Part Number: mpc8568e
• Description: Mpc8568e Powerquicc Iii Processor
• Manufacturer: Freescale Semiconductor, Inc

Ordering Information
25.9.2
25.9.2.1
If the high speed interface is not used at all, then SCOREVDD/XVDD/AV
all receiver inputs should be tied to the GND as well. This includes:
25.9.2.2
If the high-speed SerDes interface is partly unused, any of the unused receiver pins should be terminated
as follows:
During HRESET/POR, the high-speed interface must be in Serial RapidIO mode and/or PCI Express mode
according to the state of the PE[8:10]. Software must disable this mode through DEVDISR[SRIO] or
DEVDISR[PCIE] accordingly during software initialization.
26 Ordering Information
Please contact your local Freescale sales office or regional marketing team for order information.
136
•
•
•
•
•
•
•
•
•
•
•
SD_TX[7:0]
SD_RX[7:0]
SD_RX[7:0]
SD_REF_CLK
SD_REF_CLK
SD_RX_CLK
SD_RX_FRM_CTL
SD_RX[7:0] = tied to SCOREGND
SD_RX[7:0] = tied to SCOREGND
SD_REF_CLK = tied to SCOREGND
SD_REF_CLK = tied to SCOREGND
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
Unused input
SerDes block power not supplied
SerDes Interface Partly used
Power down the unused lane through SERDESCR1[0:7] register
(offset = 0xE_0F08) (This prevents the oscillations and holds the receiver
output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.
NOTE
DD_SRDS
Freescale Semiconductor
can be tied to GND,