mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 231

• Manufacturer Part Number: mc68hc912bd32
• Description: 16-bit Device Composed Of Standard On-chip Peripherals
• Manufacturer: Freescale Semiconductor, Inc

ATDTSTH — ATD Test Register
ATDTSTL — ATD Test Register
9-adc
RESET:
RESET:
SAR9
SAR1
Bit 7
Bit 7
0
0
SAR8
SAR0
6
0
6
0
SCF — Sequence Complete Flag
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight
Conversions
CCF[7:0] — Conversion Complete Flags
This bit is set at the end of the conversion sequence when in the
single conversion sequence mode (SCAN = 0 in ATDCTL5) and is set
at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is
cleared when a write is performed to ATDCTL5 to initiate a new
conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
This 3-bit value reflects the contents of the conversion counter pointer
in a four or eight count sequence. This value also reflects which result
register will be written next, indicating which channel is currently
being converted.
Each of these bits are associated with an individual ATD result
register. For each register, this bit is set at the end of conversion for
the associated ATD channel and remains set until that ATD result
register is read. It is cleared at that time if AFFC bit is set, regardless
of whether a status register read has been performed (i.e., a status
register read is not a pre-qualifier for the clearing mechanism when
AFFC = 1). Otherwise the status register must be read to clear the
flag.
Freescale Semiconductor, Inc.
For More Information On This Product,
SAR7
RST
5
0
5
0
Go to: www.freescale.com
Analog to Digital Converter
TSTOUT
SAR6
4
0
4
0
SAR5
TST3
3
0
3
0
SAR4
TST2
2
0
2
0
SAR3
TST1
1
0
1
0
MC68HC912BD32 Rev 1.0
Analog to Digital Converter
SAR2
TST0
Bit 0
Bit 0
0
0
ATD Registers
$0068
$0069