mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 228

• Manufacturer Part Number: mc68hc912bd32
• Description: 16-bit Device Composed Of Standard On-chip Peripherals
• Manufacturer: Freescale Semiconductor, Inc

ATDCTL5 — ATD Control Register 5
Analog to Digital Converter
MC68HC912BD32 Rev 1.0
RESET:
Bit 7
0
0
S8CM
6
0
S8CM — Select 8 Channel Mode
Prescale Value
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become
2. Minimum conversion frequency is 500 KHz. Minimum P clock divisor value will become
ATD module clock. The divide-by-two circuit insures symmetry of the
output clock signal. Clearing these bits causes the prescale value
default to one which results in a 2 prescale factor. This signal is then
fed into the 2 logic. The reset state divides the P clock by a total of
four and is appropriate for nominal operation between 2 MHz and 8
MHz bus rate. For operation at 10 MHz this value must be
reprogrammed first to
shows the divide-by operation and the appropriate range of system
clock frequencies.
The ATD control register 5 is used to select the conversion modes,
the conversion channel(s), and initiate conversions.
Read or write anytime. A write to ATDCTL5 initiates a new conversion
sequence. If a conversion sequence is in progress when a write
occurs, that sequence is aborted and the SCF and CCF bits are reset.
Freescale Semiconductor, Inc.
maximum conversion rate that can be used on this ATD module.
minimum conversion rate that this ATD can perform.
For More Information On This Product,
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
SCAN
5
0
Go to: www.freescale.com
Analog to Digital Converter
MULT
Total Divisor
Table 53 Clock Prescaler Values
4
0
10
12
14
16
2
4
6
8
6
CD
or greater before using the ATD.
3
0
Max P Clock
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
CC
4 MHz
8 MHz
2
0
Do Not Use
(1)
CB
1
0
Min P Clock
Bit 0
CA
0
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
Table 53
(2)
$0065
6-adc