mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 76

• Manufacturer Part Number: mc68hc912d60c
• Description: Hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Operating Modes and Resource Mapping
Technical Data
76
ESTR — E Clock Stretch Enable
IVIS — Internal Visibility
EBSWAI — External Bus Module Stop in Wait Control
Determines if the E Clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
ESTR is always 1 in expanded modes since it is required for address
and data bus de-multiplexing and must follow stretched cycles.
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during
non-visible internal accesses (IVIS=0).
Normal modes: write once; Special modes: write anytime. Read
anytime.
This bit determines whether internal ADDR, DATA, R/W and LSTRB
signals can be seen on the external bus during accesses to internal
locations. In Special Narrow Mode if this bit is set and an internal
access occurs the data will appear wide on Ports A and B. This serves
the same function as the EMD bit of the non-multiplexed versions of
the HC12 and allows for emulation. Visibility is not available when the
part is operating in a single-chip mode.
0 = No visibility of internal bus operations on external bus.
1 = Internal bus operations are visible on external bus.
Normal modes: write once; Special modes: write anytime EXCEPT
the first time. Read anytime.
This bit controls access to the external bus interface when in wait
mode. The module will delay before shutting down in wait mode to
allow for final bus activity to complete.
0 = External bus and registers continue functioning during wait mode.
1 = External bus is shut down during wait mode.
Normal modes: write anytime; Special modes: write never. Read
anytime.
Operating Modes and Resource Mapping
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor