mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 19

• Manufacturer Part Number: mc68hc912d60c
• Description: Hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Technical Data — MC68HC912D60A
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Table
1-1
1-2
2-1
2-2
3-1
3-2
3-3
3-4
4-1
5-1
5-2
5-3
5-4
8-1
8-2
8-3
8-4
9-1
9-2
11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . . 155
11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . . 155
11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . . 212
13-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 222
13-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 222
14-1 Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 238
14-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .238
Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Development Tools Ordering Information. . . . . . . . . . . . . . . . . 28
M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . . 34
Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . . 35
MC68HC912D60A Power and Ground Connection Summary . 44
MC68HC912D60A Signal Description Summary . . . . . . . . . . . 50
MC68HC912D60A Port Description Summary . . . . . . . . . . . . . 59
Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . . 60
MC68HC912D60A Register Map . . . . . . . . . . . . . . . . . . . . . . . 62
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EEDIV Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . 112
Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Interrupt Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . . 128
Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
List of Tables
Title
List of Tables
Technical Data
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