mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 238
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mc68hc912d60c
Manufacturer Part Number
mc68hc912d60c
Description
Hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC912D60C.pdf
(460 pages)
- Current page: 238 of 460
- Download datasheet (5Mb)
Enhanced Capture Timer
TCTL3 — Timer Control Register 3
TCTL4 — Timer Control Register 4
Technical Data
238
RESET:
RESET:
EDG7B
EDG3B
Bit 7
Bit 7
0
0
EDG7A
EDG3A
6
0
6
0
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
These eight pairs of control bits configure the input capture edge
detector circuits.
EDG6B
EDG2B
5
0
EDGnB
5
0
Table 14-2. Edge Detector Circuit Configuration
OMn
0
0
1
1
0
0
1
1
Table 14-1. Compare Result Output Action
Enhanced Capture Timer
EDG6A
EDG2A
4
0
EDGnA
4
0
OLn
0
1
0
1
0
1
0
1
EDG5B
EDG1B
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
3
0
3
0
Timer disconnected from output pin logic
Clear OCn output line to zero
Set OCn output line to one
EDG5A
EDG1A
Toggle OCn output line
2
0
2
0
Configuration
Action
EDG4B
EDG0B
MC68HC912D60A — Rev. 3.1
1
0
1
0
Freescale Semiconductor
EDG4A
EDG0A
Bit 0
Bit 0
0
0
$008A
$008B
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