mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 237

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mc68hc912d60c

Manufacturer Part Number
mc68hc912d60c
Description
Hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
TQCR — Reserved
TCTL1 — Timer Control Register 1
TCTL2 — Timer Control Register 2
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
RESET:
RESET:
Bit 7
OM3
OM7
Bit 7
Bit 7
NOTE:
0
0
0
OL3
OL7
6
0
6
0
6
0
Read or write anytime.
OMn — Output Mode
OLn — Output Level
To enable output action by OMn and OLn bits on the timer port, the
corresponding bit in OC7M should be cleared.
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
OM6
OM2
5
0
5
0
5
0
MCCNT register ($B6, $B7) clears the MCZF flag in the
MCFLG register ($A7). This has the advantage of eliminating
software overhead in a separate clear sequence. Extra care is
required to avoid accidental flag clearing due to unintended
accesses.
Enhanced Capture Timer
OL6
OL2
4
0
4
0
4
0
OM5
OM1
3
0
3
0
3
0
OL5
OL1
2
0
2
2
0
0
OM0
OM4
1
0
1
0
1
0
Enhanced Capture Timer
Bit 0
Bit 0
Bit 0
OL0
OL4
0
0
0
Timer Registers
Technical Data
$0087
$0088
$0089
237

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