mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 254

• Manufacturer Part Number: mc68hc912d60c
• Description: Hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Capture Timer
TIMTST — Timer Test Register
Technical Data
254
RESET:
BIT 7
0
0
6
0
0
Read: any time
Write: only in special mode (SMOD = 1).
TCBYP — Main Timer Divider Chain Bypass
0 = Queue Mode of Input Capture is enabled.
1 = Latch Mode is enabled. Latching function occurs when
0 = Normal operation
1 = For testing only. The 16-bit free-running timer counter is divided
5
0
0
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
into two 8-bit halves and the prescaler is bypassed. The clock
drives both halves directly.
When the high byte of timer counter TCNT ($84) overflows
from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.
Enhanced Capture Timer
4
0
0
3
0
0
2
0
0
Buffered IC
TCBYP
MC68HC912D60A — Rev. 3.1
1
0
Freescale Semiconductor
Channels).
BIT 0
0
0
$00AD