mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 335

• Manufacturer Part Number: mc68hc912d60c
• Description: Hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

17.13.6 msCAN12 Receiver Flag Register (CRFLG)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
CRFLG
$0104
RESET
0
0
0
0
1
.
.
W
R
0
0
0
0
1
.
.
NOTE:
WUPIF
Bit 7
0
0
0
1
1
1
.
.
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (Tq) clock cycles per bit (as
shown above).
The CBTR1 register can only be written if the SFTRES bit in CMCR0 is set
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can only be cleared
when the condition which caused the setting is no more valid. Writing a 0
has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset clears the register.
WUPIF — Wake-up Interrupt Flag
RWRNIF
If the msCAN12 detects bus activity while in SLEEP Mode, it sets the
WUPIF flag. If not masked, a Wake-Up interrupt is pending while this
flag is set.
6
0
0 = No wake-up activity has been observed while in SLEEP Mode.
1 = msCAN12 has detected activity on the bus and requested
0
1
0
1
1
.
.
Table 17-8. Time segment values
wake-up.
BitTime
TWRNIF
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
5
0
MSCAN Controller
=
.
.
------------------------------------------ - number
f CGMCANCLK
RERRIF
Presc value
4
0
⋅
TSEG22 TSEG21 TSEG20 Time segment 2
TERRIF
0
0
1
.
.
3
0
•
Programmer’s Model of Control Registers
0
0
1
.
.
BOFFIF
Þ
2
0
of
Þ
TimeQuanta
0
1
1
.
.
OVRIF
1
0
MSCAN Controller
2 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
Technical Data
.
.
Bit 0
RXF
0
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