ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 53

• Manufacturer Part Number: ez80l92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 12. Vectored Interrupt Operation (Continued)
PS013014-0107
Memory
Mode
ADL Mode
Non-maskable Interrupts
ADL
Bit
An active Low input on the NMI pin generates an interrupt request to the eZ80 CPU. This
non-maskable interrupt is always serviced by the eZ80 CPU, regardless of the state of the
Interrupt Enable flags (IEF1 and IEF2). The non-maskable interrupt is prioritized higher
than all maskable interrupts. The response of the eZ80 CPU to a non-maskable interrupt is
described in detail in eZ80
1
MADL
Bit
1
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
The ADL mode bit remains set to 1.
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}.
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
The ending Program Counter is { 00h, PC[15:0] }.
The interrupt service routine must end with RETI.L
←
←
0
0
®
CPU User Manual (UM0077).
Product Specification
Interrupt Controller
eZ80L92 MCU
47