ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 119

• Manufacturer Part Number: ez80l92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS013014-0107
UART Interrupt Identification Registers
The Read-Only UARTx_IIR register allows you to check whether the FIFO is enabled and
the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL
registers. See
Table 57. UART Interrupt Identification Registers (UART0_IIR = 00C2h, UART1_IIR
Bit
Position
1
TIE
0
RIE
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:6]
FSTS
[5:4]
[3:1]
INSTS
0
INTBIT
= 00D2h)
Table 57
Value Description
000–110 Interrupt Status Code
Value
0
1
0
1
00
00
11
0
1
and
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the
transmit FIFO/buffer is empty indicating no more bytes
available for transmission.
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled.
Interrupt is generated if the FIFO/buffer contains data ready to
be read or if the receiver times out.
Table
R
7
0
Description
FIFO is disabled.
FIFO is enabled.
Reserved
The code indicated in these three bits is valid only if INTBIT
is 0. If two internal interrupt sources are active and their
respective enable bits are High, only the higher priority
interrupt is seen by the application. The lower-priority
interrupt code is indicated only after the higher-priority
interrupt is serviced.
There is an active interrupt source within the UART.
There is not an active interrupt source within the UART.
58.
R
6
0
R
5
0
Universal Asynchronous Receiver/Transmitter
Table 58
R
4
0
lists the interrupt status codes.
R
3
0
Product Specification
R
2
0
eZ80L92 MCU
R
1
0
R
0
1
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