ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 120

• Manufacturer Part Number: ez80l92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS013014-0107
Table 58. UART Interrupt Status Codes
UART FIFO Control Registers
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See
Table 59. UART FIFO Control Registers (UART0_FCTL = 00C2h, UART1_FCTL =
INSTS Value
011
010
110
001
000
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:6]
TRIG
[5:3]
00D2h)
Table
Value Description
000
00
01
10
11
59.
Priority
Highest
Second
Third
Fourth
Lowest
Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
Reserved.
W
7
0
Interrupt Type
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
Transmit Buffer Empty
Modem Status
W
6
0
W
5
0
Universal Asynchronous Receiver/Transmitter
W
4
0
W
3
0
Product Specification
W
2
0
eZ80L92 MCU
W
1
0
W
0
0
114