dac1005d650 NXP Semiconductors, dac1005d650 Datasheet - Page 29

• Manufacturer Part Number: dac1005d650
• Description: Dual 10-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1005D650_1
Product data sheet
10.11 Digital offset adjustment
Table 36.
Default settings are shown highlighted.
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see
“DAC_A_Cfg_2 register (address 0Ah) bit
(register 0Dh; see
the fine variation of the full-scale current (see
Table 37.
Default settings are shown highlighted.
The coding of the fine gain adjustment is two’s complement.
When the DAC1005D650 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common mode level at the output of the DAC. It
adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[8:0] (register 09h; see
register (address 09h) bit description”
register (address 0Bh) bit
Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description”
Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit
variation of the digital offset (see
DAC_GAIN_COARSE[3:0]
Decimal
8
9
10
11
12
13
14
15
DAC_GAIN_FINE[5:0]
Decimal
...
0
...
+31
32
I
I
O(fs)
O(fs)
coarse adjustment
fine adjustment
Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit
Rev. 01 — 28 July 2009
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
description”) and to “DAC_B_OFFSET[8:0]” (register 0Ch; see
Binary
1000
1001
1010
1011
1100
1101
1110
1111
Two’s complement
10 0000
...
00 0000
...
01 1111
Table 38 “Digital offset
…continued
and register 0Bh; see
description”) and to DAC_B_GAIN_FINE[5:0]
Table 37 “I
description”) define the range of
adjustment”).
O(fs)
DAC1005D650
I
12.8
14.2
15.6
17.0
18.5
20.0
21.0
22.0
Delta I
...
0
...
+10 %
Table 21 “DAC_A_Cfg_3
O(fs)
fine
10 %
and register 0Eh; see
Table 19 “DAC_A_Cfg_1
(mA)
adjustment”).
O(fs)
Table 20
description”) define
© NXP B.V. 2009. All rights reserved.
29 of 41