dac1005d650 NXP Semiconductors, dac1005d650 Datasheet
dac1005d650
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dac1005d650 Summary of contents
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... In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1005D650 also includes and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. ...
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... Product data sheet Dual 10-bit DAC 650 Msps and 8 interpolating Description plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad Rev. 01 — 28 July 2009 DAC1005D650 Version SOT638-1 © NXP B.V. 2009. All rights reserved ...
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... Block diagram DAC1005D650 18 to 25, FIR1 28, 29 LATCH dual port/ interleaved data modes FIR1 41, 42 LATCH CLKP CLOCK GENERATOR/ 9 PLL CLKN 66 RESET_N Fig 1. Block diagram SDO SCS_N SDIO SCLK SPI NCO ...
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... Fig 2. Pin configuration DAC1005D650_1 Product data sheet Dual 10-bit DAC 650 Msps and 8 interpolating DAC1005D650HW AGND Rev. 01 — 28 July 2009 DAC1005D650 75 V DDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 V DDA(1V8 DDA(1V8) 69 GAPOUT 68 VIRES 67 d ...
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... P digital supply voltage 1 digital ground 34 I not connected 35 I not connected 36 P digital supply voltage 1 digital ground 38 - test mode 2 (to connect to DGND digital ground Rev. 01 — 28 July 2009 DAC1005D650 © NXP B.V. 2009. All rights reserved ...
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... O complementary auxiliary DAC B output current 74 O auxiliary DAC B output current 75 P analog supply voltage 3 analog ground 77 P analog supply voltage 1 analog ground 79 P analog supply voltage 1.8 V Rev. 01 — 28 July 2009 DAC1005D650 © NXP B.V. 2009. All rights reserved ...
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... analog ground 95 P analog supply voltage 1 analog ground 97 P analog supply voltage 1 analog ground 99 P analog supply voltage 1.8 V 100 G analog ground [ analog ground Rev. 01 — 28 July 2009 DAC1005D650 © NXP B.V. 2009. All rights reserved ...
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... CLKP, CLKN, VIRES and GAPOUT referenced to AGND pins Q0, SDO, SDIO, SCLK, SCS_N and RESET_N referenced to GNDIO pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to AGND Conditions Rev. 01 — 28 July 2009 DAC1005D650 Min Max Unit 0.5 +4.6 V 0.5 +4 ...
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... NCO on; all MHz 640 Msps interpolation; NCO low power on Power-down mode full power-down; all V DD DAC A and DAC B Sleep mode; 8 interpolation; NCO on Rev. 01 — 28 July 2009 DAC1005D650 = 20 mA; maximum sample rate; PLL on; O(fs) [1] Test Min Typ Max I 3.0 3.3 3.6 I 3.0 3.3 3 ...
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... register value = 00h default register compliance range guaranteed amb external voltage 1.25 V Rev. 01 — 28 July 2009 DAC1005D650 = mA; maximum sample rate; PLL on; L O(fs) [1] Test Min Typ [3] C 825 - [3] C 100 - 0.5 ...
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... MHz at 0 dBFS MHz at 0 dBFS 160 MHz 640 Msps; data data MHz at 0 dBFS o Rev. 01 — 28 July 2009 DAC1005D650 = 20 mA; maximum sample rate; PLL on; O(fs) [1] Test Min Typ Max ...
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... MHz 2 carriers MHz 4 carriers MHz f = 640 Msps; 8 interpolation MHz at 0 dBFS o noise shaper disabled noise shaper enabled Figure 8). Rev. 01 — 28 July 2009 DAC1005D650 = mA; maximum sample rate; PLL on; O(fs) [1] Test Min Typ Max ...
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... NXP Semiconductors 10. Application information 10.1 General description The DAC1005D650 is a dual 10-bit DAC operating 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary weighted sub-DAC. With an input data rate 160 MHz, and a maximum output sampling rate of 650 Msps, the DAC1005D650 allows more fl ...
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... Table 9 “Register allocation t w(RESET_N su(SCS_N SCLK 50 % SDIO h(SDIO) t su(SDIO) SPI timing diagram Rev. 01 — 28 July 2009 DAC1005D650 Number of bytes 1 byte transferred 2 bytes transferred 3 bytes transferred 4 bytes transferred map”. t w(SCLK ...
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... Dual 10-bit DAC 650 Msps and 8 interpolating SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Rev. 01 — 28 July 2009 DAC1005D650 Table 8. Min Typ Max - - ...
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Table 9. Register allocation map Address Register name R/W Bit definition b7 0 00h COMMon R/W 3W_SPI 1 01h TXCFG R/W NCO_ON 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W 5 05h FREQNCO_UISB R/W 6 ...
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... R/W GAP_PD R/W TXCFG register (address 01h) bit description Symbol Access Value Description NCO_ON R/W NCO_LP_SEL R/W Rev. 01 — 28 July 2009 DAC1005D650 serial interface bus type 0 4 wire SPI 1 3 wire SPI serial interface reset 0 no reset 1 performs a reset on all registers except 00h data input latch ...
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... FREQNCO_LSB register (address 03h) bit description Symbol Access Value Description R/W FREQNCO_LISB register (address 04h) bit description Symbol Access Value Description R/W Rev. 01 — 28 July 2009 DAC1005D650 …continued modulation 000 dual DAC: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion ...
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... Symbol Access Value Description R/W DAC_A_Cfg_3 register (address 0Bh) bit description Symbol Access Value R/W Rev. 01 — 28 July 2009 DAC1005D650 - upper intermediate 8 bits for the NCO frequency setting - most significant 8 bits for the NCO frequency setting - lower 8 bits for the NCO phase setting - most signifi ...
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... Symbol Access Value AUX_A[9:2] R/W - DAC_A_Aux_LSB register (address 1Bh) bit description Symbol Access Value AUX_A_PD R/W AUX_A[1:0] R/W Rev. 01 — 28 July 2009 DAC1005D650 DAC B power off DAC B Sleep mode 0 disabled 1 enabled lower 3 bits for the DAC B offset - less significant 2 bits for the DAC B gain ...
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... Table 29. Default settings are shown highlighted. Bit 10.3 Input data The setting applied to MODE_SEL (register 00h[3]; see whether the DAC1005D650 operates in the Dual-port mode or in the Interleaved mode (see Table Table 30. Bit 3 setting 0 1 10.3.1 Dual-port mode The data input for Dual-port mode operation is shown in DAC has its own independent data input ...
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... Q. After this, the data is distributed alternately between both channels. 10.4 Input clock The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see can also be interfaced with CML (see ...
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... NXP Semiconductors Fig 8. Fig 9. 10.5 Timing The DAC1005D650 can operate at an update rate (f data rate (f diagram”. (CLKP-CLKN) Fig 10. Input timing diagram The typical performances are measured duty cycle but any timing within the limits of the characteristics will not alter the performance. ...
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... Table 32 “Sample clock phase and polarity Sample clock phase and polarity examples Input data rate Interpolation (MHz 160 2 160 4 160 8 Rev. 01 — 28 July 2009 DAC1005D650 Interpolation Update rate PLL_DIV[1:0] (Msps) 2 320 01 (/4) 4 640 01 (/4) 8 640 10 (/8) 2 320 00 (/2) 4 ...
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... NXP Semiconductors 10.6 FIR filters The DAC1005D650 integrates three selectable Finite Impulse Response (FIR) filters which enable the device to use interpolation rates All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in coeffi ...
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... Dual 10-bit DAC 650 Msps and 8 interpolating ---------------- - MHz when f NCO ---------------- - 5 2 Table 34 “Inversion filter Rev. 01 — 28 July 2009 DAC1005D650 = 640 Msps and the default phase coefficients”. (1) (2) © NXP B.V. 2009. All rights reserved ...
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... The output current depends on the digital input data: I IOUTP I IOUTN The setting applied to CODING (register 00h[2]; see defines whether the DAC1005D650 operates with a binary input or a two’s complement input. Table 35 “DAC transfer function” when I O(fs) Table 35. Data (Decimal) 0 ... ...
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... Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit I coarse adjustment O(fs) Binary 0000 0001 0010 0011 0100 0101 0110 0111 Rev. 01 — 28 July 2009 DAC1005D650 (1 %) connected to O(fs) REF. BANDGAP DAC CURRENT SOURCES ARRAY 001aaj816 10 %. Table 20 and register 0Bh; see description”) and to DAC_B_GAIN Table 36 “I ...
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... The coding of the fine gain adjustment is two’s complement. 10.11 Digital offset adjustment When the DAC1005D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. ...
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... Analog output The DAC1005D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using a load resistor R ...
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... NXP Semiconductors 10.13 Auxiliary DACs The DAC1005D650 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] define the offset data. ...
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... DC interface to an AQM When the system operation requires to keep the DC component of the spectrum, the DAC1005D650 can use a DC interface to connect to an Analog Quadrature Modulator (AQM). In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. ...
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... BBP/BBN 1 i(cm) provides an example of a connection to an AQM with a 3.3 V 3.3 V (1) 54.9 54.9 237 IOUTnP 237 IOUTnN 1.27 k 1.27 k (1) IOUTnP/IOUTnN 2. o(cm) (2) BBP/BBN 3 i(cm) Rev. 01 — 28 July 2009 DAC1005D650 AQM (V = 1.7 V) i(cm) (2) BBP BBN 768 768 = 1.98 V o(dif)(p-p) = 1.26 V i(dif)(p-p) 001aaj541 i(cm) AQM ( i(cm) (2) 750 750 BBP BBN = 1 ...
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... IOUTnP 237 IOUTnN 634 k 634 k AUXnP AUXnN 442 k 442 k (1) IOUTnP/IOUTnN 2. o(cm) (2) BBP/BBN 3 i(cm) Rev. 01 — 28 July 2009 DAC1005D650 AQM (V = 1.7 V) i(cm) (2) BBP BBN 698 698 51.1 51.1 = 1.94 V o(dif)(p-p) = 1.23 V; offset correction i(dif)(p-p) 001aaj543 AQM using auxiliary DACs i(cm) AQM ( i(cm) ...
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... DACs, the input common mode level of the AQM, and the range of offset correction required. 10.14.3 AC interface to an AQM When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground, the DAC1005D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 18 input level when using auxiliary DACs. ...
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... Product data sheet Dual 10-bit DAC 650 Msps and 8 interpolating Alternative parts Description dual 12-bit DAC dual 14-bit DAC Rev. 01 — 28 July 2009 DAC1005D650 Sampling frequency up to 650 Msps up to 650 Msps © NXP B.V. 2009. All rights reserved ...
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... scale (1) ( 0.20 14.1 7.1 14.1 7.1 0.5 0.09 13.9 6.1 13.9 6.1 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 28 July 2009 DAC1005D650 detail 16.15 16.15 0.75 1 0.2 0.08 0.08 15.85 15.85 0.45 EUROPEAN PROJECTION SOT638 (1) ( ...
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... Phase-Locked Loop Spurious-Free Dynamic Range Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Upper Intermediate Significant Byte Wideband Code Division Multiple Access Worldwide Interoperability for Microwave Access Rev. 01 — 28 July 2009 DAC1005D650 © NXP B.V. 2009. All rights reserved ...
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... Product data sheet Dual 10-bit DAC 650 Msps and 8 interpolating nd rd and 3 order components) are defined below. Data sheet status Product data sheet Rev. 01 — 28 July 2009 DAC1005D650 . offset Change notice Supersedes - - © NXP B.V. 2009. All rights reserved. nd order ...
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... Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 28 July 2009 DAC1005D650 © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com DAC1005D650 All rights reserved. Date of release: 28 July 2009 Document identifier: DAC1005D650_1 ...